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1. 发明申请

US20080197449A1 WIRING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD AND DEVICE FOR DESIGNING THE SAME 审中-公开
标题翻译：半导体集成电路装置的布线结构及其设计方法和装置
公开(公告)号：US20080197449A1
公开(公告)日：2008-08-21
申请号：US12035230
申请日：2008-02-21
申请人： Takayuki ARAKI , Junichi Shimada , Hirokazu Ogawa , Kazuhiko Fujimoto , Tsutomu Fujii , Takuya Yasui
发明人： Takayuki ARAKI , Junichi Shimada , Hirokazu Ogawa , Kazuhiko Fujimoto , Tsutomu Fujii , Takuya Yasui
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for designing a wiring structure of a wiring layer of a semiconductor integrated circuit device. The method includes a wire width detecting step of detecting a wire width of each wire in a wiring pattern of layout data, a wire identifying step of identifying a wire having a predetermined wire width or more based on a result of detection by the wire width detecting step, a wiring pitch detecting step of detecting a wiring pitch between the wire identified by the wire identifying step and another wire, and an air gap-forbidden region forming and removing step of forming or removing an air gap-forbidden region, depending on a result of detection by the wiring pitch detecting step.
摘要翻译：提供一种用于设计半导体集成电路器件的布线层的布线结构的方法。该方法包括：线宽检测步骤，检测布线数据的布线图案中的每条线的线宽;线识别步骤，基于线宽检测的检测结果识别具有预定线宽或更大的线的线; 步骤，检测由线识别步骤识别的线与另一线之间的布线间距的接线间距检测步骤以及形成或除去气隙禁止区域的气隙禁止区形成和移除步骤，通过布线间距检测步骤的检测结果。

2. 发明授权

US08028264B2 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US08028264B2
公开(公告)日：2011-09-27
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： G06F17/50
CPC分类号： H01L27/0203 , H01L27/118
摘要： A semiconductor device including a plurality of cells having an antenna protection element and a cell other than the antenna protection element; and a first dummy pattern and a second dummy pattern arranged in a layer above the plurality of cells. Further, the first dummy pattern overlaps with the antenna protection element, the second dummy pattern overlaps with the cell other than the antenna protection element, and a first layout rule of the first dummy pattern is different from a second layout rule of the second dummy pattern.
摘要翻译：一种半导体器件，包括具有天线保护元件和除天线保护元件之外的单元的多个单元; 以及布置在所述多个单元上方的层中的第一虚设图案和第二虚设图案。此外，第一伪图案与天线保护元件重叠，第二虚设图案与天线保护元件以外的单元重叠，并且第一虚设图案的第一布局规则与第二虚设图案的第二布局规则不同。

3. 发明申请

US20070252258A1 Semiconductor device and semiconductor device layout designing method 有权
标题翻译：半导体器件和半导体器件布局设计方法
公开(公告)号：US20070252258A1
公开(公告)日：2007-11-01
申请号：US11790736
申请日：2007-04-27
申请人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
发明人： Junichi Shimada , Fumihiro Kimura , Yoichi Matsumura , Takako Ohashi , Nobuyuki Iwauchi , Takeya Fujino , Takayuki Araki , Yukiji Hashimoto , Takuya Yasui , Hirofumi Taguchi
IPC分类号： H01L23/02 , G08B13/14 , H01Q9/04
CPC分类号： H01L27/0203 , H01L27/118
摘要： In each wiring layer in which wirings connected to a gate is formed, wirings are routed so as not to cover the active region of an antenna protection element. A wiring formed in an upper wiring layer is routed so as to cover at least a part of the active region of the antenna protection element.
摘要翻译：在形成连接到栅极的布线的每个布线层中，布线被布线成不覆盖天线保护元件的有源区。形成在上布线层中的布线被布线以覆盖天线保护元件的有源区域的至少一部分。

4. 发明授权

US07698671B2 Method for designing semiconductor integrated circuits having air gaps. 失效
标题翻译：具有气隙的半导体集成电路的设计方法。
公开(公告)号：US07698671B2
公开(公告)日：2010-04-13
申请号：US11942384
申请日：2007-11-19
申请人： Tsutomu Fujii , Hirofumi Miyashita , Hiromasa Fukazawa , Tatsuo Gou , Takuya Yasui
发明人： Tsutomu Fujii , Hirofumi Miyashita , Hiromasa Fukazawa , Tatsuo Gou , Takuya Yasui
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068
摘要： Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.
摘要翻译：接收关于半导体集成电路的电路数据，关于半导体集成电路的设计的设计限制，关于电路数据中的气隙创建的气隙信息，以及指定气隙容积值的允许范围的气隙容积约束。计算根据气隙信息在电路数据中产生的气隙的体积值的总和。在检测到计算出的气隙体积值的总和超出由气隙体积约束规定的容许范围之外时，对电路数据进行优化，使得满足设计约束，并且气隙体积值的总和在其内允许范围。

5. 发明申请

US20080120583A1 METHOD AND PROGRAM FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT, METHOD AND PROGRAM FOR SUPPORTING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD AND PROGRAM FOR CALCULATING WIRING PARASITIC CAPACITANCE 失效
标题翻译：用于设计半导体集成电路的方法和程序，用于支持半导体集成电路设计的方法和程序，以及用于计算接线对准电容的方法和程序
公开(公告)号：US20080120583A1
公开(公告)日：2008-05-22
申请号：US11942384
申请日：2007-11-19
申请人： Tsutomu Fujii , Hirofumi Miyashita , Hiromasa Fukazawa , Tatsuo Gou , Takuya Yasui
发明人： Tsutomu Fujii , Hirofumi Miyashita , Hiromasa Fukazawa , Tatsuo Gou , Takuya Yasui
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Circuit data on a semiconductor integrated circuit, design constraints as to design of the semiconductor integrated circuit, air gap information on air gap creation in the circuit data, and an air gap volume constraint specifying an allowable range for an air gap volume value are received. The sum total of the values of the volumes of air gaps created in the circuit data according to the air gap information is calculated. Upon detection that the calculated sum total of the air gap volume values falls outside the allowable range specified by the air gap volume constraint, the circuit data is optimized so that the design constraints are satisfied and the sum total of the air gap volume values falls within the allowable range.
摘要翻译：接收关于半导体集成电路的电路数据，关于半导体集成电路的设计的设计限制，关于电路数据中的气隙创建的气隙信息，以及指定气隙容积值的允许范围的气隙容积约束。计算根据气隙信息在电路数据中产生的气隙的体积值的总和。在检测到计算出的气隙体积值的总和超出由气隙体积约束规定的容许范围之外时，对电路数据进行优化，使得满足设计约束，并且气隙体积值的总和在其内允许范围。

6. 发明申请

US20120010342A1 ANTIFOULING COATING COMPOSITION, ANTIFOULING COATING FILM FORMED BY USE OF THE COMPOSITION, COATED OBJECT HAVING THE COATING FILM THEREON, AND METHOD OF ANTIFOULING TREATMENT BY FORMING THE COATING FILM 审中-公开
标题翻译：防涂层组合物，使用组合物形成的防粘涂膜，其涂布膜的涂覆对象，以及通过形成涂膜进行抗蚀处理的方法
公开(公告)号：US20120010342A1
公开(公告)日：2012-01-12
申请号：US13257532
申请日：2010-06-01
申请人： Tsuyoshi Iwamoto , Takuya Yasui , Hitoshi Kitamura , Takayoshi Fujimoto
发明人： Tsuyoshi Iwamoto , Takuya Yasui , Hitoshi Kitamura , Takayoshi Fujimoto
IPC分类号： C09D5/16 , C09D129/12
CPC分类号： C09D5/1668 , C09D133/14
摘要： The present invention provides an antifouling coating material which can be used to form an antifouling coating film excellent in long-term antifouling performance and physical properties, and which is excellent in long-term storage stability. The present invention provides an antifouling coating composition containing a copolymer [A] obtained by copolymerizing a monomer represented by a general formula (1) (wherein, X represents acryloyloxy, methacryloyloxy, crotonoyloxy, or isocrotonoyloxy, R1 represents a hydrogen atom or methyl, and R2 represents an alkyl group having a carbon number of 1 to 6), and a polymerizable monomer represented by a general formula (2) (wherein, R3 represents a hydrogen atom or methyl, R4 represents an alkyl group having a carbon number of 1 to 10, or an alkyl group having a carbon number of 2 to 5 to which an alkoxy group having a carbon number of 1 to 4 is bonded.).
摘要翻译：本发明提供一种防污涂料，其可用于形成长期防污性能和物理性能优异的防污涂膜，并且其长期保存稳定性优异。本发明提供一种防污涂料组合物，其含有通过使通式（1）表示的单体（其中X表示丙烯酰氧基，甲基丙烯酰氧基，巴豆酰氧基或异柠烷酰氧基，R1表示氢原子或甲基）和 R2表示碳数为1〜6的烷基）和由通式（2）表示的可聚合单体（其中，R3表示氢原子或甲基，R4表示碳原子数为1〜 10或碳原子数为1〜4的烷氧基的碳数为2〜5的烷基）。

7. 发明授权

US06496963B2 Delay analysis method and design assist apparatus of semiconductor circuit 失效
标题翻译：半导体电路的延迟分析方法和设计辅助装置
公开(公告)号：US06496963B2
公开(公告)日：2002-12-17
申请号：US09825367
申请日：2001-04-04
申请人： Keiichi Kurokawa , Masahiko Toyonaga , Takuya Yasui
发明人： Keiichi Kurokawa , Masahiko Toyonaga , Takuya Yasui
IPC分类号： G06F945
CPC分类号： G06F17/5031
摘要： In design of particularly large-scale, complicated semi-conductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.
摘要翻译：在特别大规模，复杂的半导体电路的设计中，使用Si制备二维图，例如，作为一个轴，Sj + Wmax + T作为另一个轴，其中T是时钟周期，Wmax是要进行信号延迟分析的电路部分的最大延迟，以及Si和Sj是用作寄存器的时钟定时以用作电路部分的输入和输出。将电路部分的延迟分析结果绘制在二维图上。另外，使用Si制作二维图，例如，作为一个轴，Sj-Wmin作为另一个轴，其中Wmin是电路部分的最小延迟，并且将电路部分的延迟分析结果绘制在该图上二维图。因此，使用所得到的二维图可以提供时钟电路的设计改进的原因或指示，保持错误和设置错误。

8. 发明申请

US20090229864A1 INSULATING CIRCUIT BOARD AND INSULATING CIRCUIT BOARD HAVING COOLING SINK 审中-公开
标题翻译：绝缘电路板和绝缘电路板有冷却水槽
公开(公告)号：US20090229864A1
公开(公告)日：2009-09-17
申请号：US11720658
申请日：2006-09-15
申请人： Yoshirou Kuromitsu , Makoto Toriumi , Yoshiyuki Nagatomo , Hiroya Ishizuka , Youichiro Baba , Tomoyuki Watanabe , Takuya Yasui
发明人： Yoshirou Kuromitsu , Makoto Toriumi , Yoshiyuki Nagatomo , Hiroya Ishizuka , Youichiro Baba , Tomoyuki Watanabe , Takuya Yasui
IPC分类号： H05K7/20 , H05K1/03
CPC分类号： H01L23/3735 , H01L23/473 , H01L2224/29111 , H01L2224/32225 , H05K1/0271 , H05K1/0306 , H05K1/09 , H05K3/0061 , H05K3/341 , H05K3/3463 , H05K2201/0352 , H05K2201/09736
摘要： An insulating circuit board includes an insulating plate, a circuit board joined to a first surface of the insulating plate, and a metal plate joined to a second surface of the insulating plate. The circuit board is formed from an Al alloy having a purity of 99.98% or more or pure Al, and the metal plate is formed from an Al alloy having a purity of 98.00% or more and 99.90% or less. The thickness (a) of the circuit board is 0.2 mm or more and 0.8 mm or less, the thickness (b) of the metal plate is 0.6 mm or more and 1.5 mm or less, and the thicknesses satisfy the expression of a/b≦1. An insulating circuit board having a cooling sink includes cooling sink joined via a second solder layer. The second solder layer contains Sn as its main component, and has a Young's modulus, 35 GPa or more, a 0.2% proof stress of, 30 MPa or more, and a tensile strength of, 40 MPa or more. The cooling sink is formed from, pure Al or an Al alloy.
摘要翻译：绝缘电路板包括绝缘板，连接到绝缘板的第一表面的电路板和连接到绝缘板的第二表面的金属板。电路板由纯度为99.98％以上的Al合金或纯Al形成，金属板由纯度为98.00％以上且99.90％以下的Al合金形成。电路板的厚度（a）为0.2mm以上且0.8mm以下，金属板的厚度（b）为0.6mm以上且1.5mm以下，厚度满足a / b <= 1。具有冷却槽的绝缘电路板包括通过第二焊料层接合的冷却水槽。第二焊料层含有Sn作为其主要成分，杨氏模量为35GPa以上，0.2％屈服应力为30MPa以上，拉伸强度为40MPa以上。冷却槽由纯Al或Al合金形成。

9. 发明申请

US20050155007A1 Automatic layout method of semiconductor integrated circuit 有权
标题翻译：半导体集成电路自动布局方法
公开(公告)号：US20050155007A1
公开(公告)日：2005-07-14
申请号：US11030297
申请日：2005-01-07
申请人： Keiichi Kurokawa , Takuya Yasui
发明人： Keiichi Kurokawa , Takuya Yasui
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5072
摘要： In a layout designing operation of LSI, while repetitions as to a timing improvement and a retry of layout designing are suppressed, a designing term is shortened. An automatic layout method of a semiconductor integrated circuit is comprised of: an initial arranging step for initially arranging a logic cell which constitutes the logic circuit; an placement base circuit optimizing step for applying a margin of a constant length to a wiring line length obtained from an placement so as to improve timing; an placement change restriction calculating step for calculating an placement change restriction corresponding to the margin of the constant length; and an incremental arranging step in which when a logic cell placement of a corrected logic circuit is improved, an placement improvement having the placement change restriction calculated based upon the placement change restriction calculating step is carried out.
摘要翻译：在LSI的布局设计操作中，抑制了对时序改进和布局设计的重试的重复，缩短了设计术语。半导体集成电路的自动布局方法包括：用于初始布置构成逻辑电路的逻辑单元的初始布置步骤; 一个放置基极电路优化步骤，用于将一个恒定长度的余量用于从放置获得的布线长度上，以便改善定时; 放置变化限制计算步骤，用于计算与所述恒定长度的所述余量相对应的放置变化限制; 以及增量排列步骤，其中当校正的逻辑电路的逻辑单元布置被改善时，执行基于所述布局改变限制计算步骤计算的所述布局改变限制的布局改进。

10. 发明授权

US06578182B2 Delay analysis method and design assist apparatus of semiconductor circuit 失效
公开(公告)号：US06578182B2
公开(公告)日：2003-06-10
申请号：US10291598
申请日：2002-11-12
申请人： Keiichi Kurokawa , Masahiko Toyonaga , Takuya Yasui
发明人： Keiichi Kurokawa , Masahiko Toyonaga , Takuya Yasui
IPC分类号： G06F945
CPC分类号： G06F17/5031
摘要： In design of particularly large-scale, complicated semiconductor circuits, a two-dimensional graph is prepared with Si, for example, as one axis and Sj+Wmax+T as the other axis where T is a clock cycle, Wmax is the maximum delay of a circuit portion to be subjected to signal delay analysis, and Si and Sj are clock timings to registers to serve as an input and an output of the circuit portion. The delay analysis results of the circuit portion are plotted on the two-dimensional graph. Also, a two-dimensional graph is prepared with Si, for example, as one axis and Sj−Wmin as the other axis where Wmin is the minimum delay of the circuit portion, and the delay analysis results of the circuit portion are plotted on this two-dimensional graph. Using the resultant two-dimensional graph, therefore, it is possible to provide the cause or an indication for design improvement of the clock circuit, a hold error, and a set-up error.

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