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1. 发明授权

US07266035B2 Self-aligned row-by-row dynamic VDD SRAM 失效
标题翻译：自对准逐行动态VDD SRAM
公开(公告)号：US07266035B2
公开(公告)日：2007-09-04
申请号：US11205466
申请日：2005-08-16
申请人： Takayasu Sakurai , Hiroshi Kawaguchi , Robert Saliba Fayez
发明人： Takayasu Sakurai , Hiroshi Kawaguchi , Robert Saliba Fayez
IPC分类号： G11C7/00
CPC分类号： G11C11/413
摘要： A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.
摘要翻译：存储单元阵列包括以矩阵形式布置的多个存储单元。字线和电源线分别连接到布置在每一行中的多个存储单元。电源线/字线控制电路连接到每个字线和每个电源线。在逐行访问多个存储单元时，控制电路提高电源线的电压，并且在所有位置的电源线的电压达到高电压之后，开始字线的激活。另一方面，在从访问状态转到非访问状态时，控制电路使字线停止，并且在字线的电压在所有位置变化为接地电压之后，改变电源的电压供电线路为低电压。

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