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1. 发明申请

US20070221924A1 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US20070221924A1
公开(公告)日：2007-09-27
申请号：US11802810
申请日：2007-05-25
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
IPC分类号： H01L29/772
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译：提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极在半导体衬底的一个表面上或在沟槽槽的底部。金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。虚拟栅电极与栅极电极和外部电线电隔离。

2. 发明申请

US20060060884A1 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US20060060884A1
公开(公告)日：2006-03-23
申请号：US11138298
申请日：2005-05-27
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
IPC分类号： H01L29/74
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译：提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极在半导体衬底的一个表面上或在沟槽槽的底部。金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。虚拟栅电极与栅极电极和外部电线电隔离。

3. 发明申请

US20060076613A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060076613A1
公开(公告)日：2006-04-13
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Malhan
IPC分类号： H01L29/94
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

4. 发明授权

US07355207B2 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07355207B2
公开(公告)日：2008-04-08
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

5. 发明授权

US07763504B2 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US07763504B2
公开(公告)日：2010-07-27
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/338
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

6. 发明授权

US07335928B2 Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each the first groove 有权
标题翻译：具有与每个第一凹槽的底部上的栅极区域欧姆接触的金属导体的半导体器件
公开(公告)号：US07335928B2
公开(公告)日：2008-02-26
申请号：US11802810
申请日：2007-05-25
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译：提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极在半导体衬底的一个表面上或在沟槽槽的底部。金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。虚拟栅电极与栅极电极和外部电线电隔离。

7. 发明授权

US07230283B2 Semiconductor device having a metal conductor in ohmic contact with the gate region on the bottom of each groove 有权
标题翻译：具有与每个凹槽底部的栅极区域欧姆接触的金属导体的半导体器件
公开(公告)号：US07230283B2
公开(公告)日：2007-06-12
申请号：US11138298
申请日：2005-05-27
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Rajesh Kumar Malhan , Tsuyoshi Yamamoto , Toshiyuki Morishita
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译：提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极在半导体衬底的一个表面上或在沟槽槽的底部。金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。虚拟栅电极与栅极电极和外部电线电隔离。

8. 发明申请

US20050258454A1 Silicon carbide semiconductor device and method for manufacturing the same 有权
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20050258454A1
公开(公告)日：2005-11-24
申请号：US11135661
申请日：2005-05-24
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/04 , H01L21/336 , H01L27/098 , H01L27/10 , H01L29/06 , H01L29/24 , H01L29/78 , H01L29/808
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

9. 发明申请

US20080153216A1 Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US20080153216A1
公开(公告)日：2008-06-26
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/82
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译：碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。

10. 发明授权

US07307313B2 Semiconductor device including a vertical field effect transistor, having trenches, and a diode 有权
标题翻译：包括具有沟槽的垂直场效应晶体管和二极管的半导体器件
公开(公告)号：US07307313B2
公开(公告)日：2007-12-11
申请号：US11206212
申请日：2005-08-18
申请人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
发明人： Takasumi Ohyanagi , Atsuo Watanabe , Toshio Sakakibara , Tsuyoshi Yamamoto , Hiroki Nakamura , Rajesh Kumar Malhan
IPC分类号： H01L29/76
CPC分类号： H01L29/1066 , H01L29/7722 , H01L29/8083
摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.
摘要翻译：半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽，沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管，在第二沟槽之间的第二表面上形成的结。

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