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    • 7. 发明授权
    • Multi-thread processor selecting threads on different schedule pattern for interrupt processing and normal operation
    • 多线程处理器在不同的调度模式下选择线程进行中断处理和正常运行
    • US08539203B2
    • 2013-09-17
    • US12585737
    • 2009-09-23
    • Koji AdachiToshiyuki Matsunaga
    • Koji AdachiToshiyuki Matsunaga
    • G06F9/46
    • G06F9/3851G06F9/3836G06F9/3867G06F9/4893Y02D10/24
    • In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule.
    • 在一个示例性方面,本发明提供一种多线程处理器,包括多个硬件线程,每个硬件线程生成独立的指令流,线程调度器,其根据第一或第二调度输出线程选择信号,线程选择 指定要在所述多个硬件线程中的下一个执行周期中执行的硬件线程;第一选择器,其根据所述线程选择信号选择所述多个硬件线程中的一个,并输出由所选择的硬件线程生成的指令;以及 执行从第一选择器输出的指令的执行管线,其中当所述多线程处理器处于第一状态时,所述线程调度器选择所述第一调度,并且当所述多线程处理器处于第二状态时,所述线程调度器 选择第二个时间表。
    • 8. 发明申请
    • Multi-thread processor
    • 多线程处理器
    • US20100082944A1
    • 2010-04-01
    • US12585737
    • 2009-09-23
    • Koji AdachiToshiyuki Matsunaga
    • Koji AdachiToshiyuki Matsunaga
    • G06F9/38
    • G06F9/3851G06F9/3836G06F9/3867G06F9/4893Y02D10/24
    • In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule.
    • 在一个示例性方面,本发明提供一种多线程处理器,包括多个硬件线程,每个硬件线程生成独立的指令流,线程调度器,其根据第一或第二调度输出线程选择信号,线程选择 指定要在所述多个硬件线程中的下一个执行周期中执行的硬件线程;第一选择器,其根据所述线程选择信号选择所述多个硬件线程中的一个,并输出由所选择的硬件线程生成的指令;以及 执行从第一选择器输出的指令的执行管线,其中当所述多线程处理器处于第一状态时,所述线程调度器选择所述第一调度,并且当所述多线程处理器处于第二状态时,所述线程调度器 选择第二个时间表。