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1. 发明授权

US08846449B2 Three-dimensional integrated circuit, processor, semiconductor chip, and manufacturing method of three-dimensional integrated circuit 有权
标题翻译：三维集成电路，处理器，半导体芯片和三维集成电路的制造方法
公开(公告)号：US08846449B2
公开(公告)日：2014-09-30
申请号：US13637729
申请日：2012-04-02
申请人： Takashi Morimoto , Takeshi Nakayama , Takashi Hashimoto
发明人： Takashi Morimoto , Takeshi Nakayama , Takashi Hashimoto
IPC分类号： H01L21/44 , H01L23/48 , H01L27/06 , H01L25/065 , H01L23/528
CPC分类号： H01L23/485 , H01L23/481 , H01L23/5223 , H01L23/5286 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2224/48 , H01L2224/48091 , H01L2224/73265 , H01L2225/06527 , H01L2225/06544 , H01L2225/06558 , H01L2225/06565 , H01L2924/13091 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： One aspect of the present invention is a three-dimensional integrated circuit 1 including a first semiconductor chip and a second semiconductor chip that are layered on each other, wherein each of (i) a wiring layer closest to an interface between the first and second semiconductor chips among wiring layers of the first semiconductor chip and (ii) a wiring layer closest to the interface among wiring layers of the second semiconductor chip includes a power conductor area and a ground conductor area, a layout of the power conductor area and the ground conductor area in the first semiconductor chip is the same as a layout of the power conductor area and the ground conductor area in the second semiconductor chip, and the power conductor area in the first semiconductor chip at least partially faces the ground conductor area in the second semiconductor chip with an insulation layer therebetween.
摘要翻译：本发明的一个方面是包括彼此层叠的第一半导体芯片和第二半导体芯片的三维集成电路1，其中，（i）最靠近第一和第二半导体之间的界面的布线层第一半导体芯片的布线层之间的芯片和（ii）最靠近第二半导体芯片的布线层之间的界面的布线层包括电源导体区域和接地导体区域，电源导体区域和接地导体的布局第一半导体芯片中的区域与第二半导体芯片中的电源导体区域和接地导体区域的布局相同，并且第一半导体芯片中的电力导体区域至少部分地面对第二半导体中的接地导体区域芯片之间具有绝缘层。

2. 发明申请

US20130037965A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT, PROCESSOR, SEMICONDUCTOR CHIP, AND MANUFACTURING METHOD OF THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
标题翻译：三维集成电路的三维集成电路，处理器，半导体芯片和三维集成电路的制造方法
公开(公告)号：US20130037965A1
公开(公告)日：2013-02-14
申请号：US13637729
申请日：2012-04-02
申请人： Takashi Morimoto , Takeshi Nakayama , Takashi Hashimoto
发明人： Takashi Morimoto , Takeshi Nakayama , Takashi Hashimoto
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L23/485 , H01L23/481 , H01L23/5223 , H01L23/5286 , H01L25/0657 , H01L27/0688 , H01L2224/16145 , H01L2224/48 , H01L2224/48091 , H01L2224/73265 , H01L2225/06527 , H01L2225/06544 , H01L2225/06558 , H01L2225/06565 , H01L2924/13091 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： One aspect of the present invention is a three-dimensional integrated circuit 1 including a first semiconductor chip and a second semiconductor chip that are layered on each other, wherein each of (i) a wiring layer closest to an interface between the first and second semiconductor chips among wiring layers of the first semiconductor chip and (ii) a wiring layer closest to the interface among wiring layers of the second semiconductor chip includes a power conductor area and a ground conductor area, a layout of the power conductor area and the ground conductor area in the first semiconductor chip is the same as a layout of the power conductor area and the ground conductor area in the second semiconductor chip, and the power conductor area in the first semiconductor chip at least partially faces the ground conductor area in the second semiconductor chip with an insulation layer therebetween.
摘要翻译：本发明的一个方面是包括彼此层叠的第一半导体芯片和第二半导体芯片的三维集成电路1，其中，（i）最靠近第一和第二半导体之间的界面的布线层第一半导体芯片的布线层之间的芯片和（ii）最靠近第二半导体芯片的布线层之间的界面的布线层包括电源导体区域和接地导体区域，电源导体区域和接地导体的布局第一半导体芯片中的区域与第二半导体芯片中的电源导体区域和接地导体区域的布局相同，并且第一半导体芯片中的电力导体区域至少部分地面对第二半导体中的接地导体区域芯片之间具有绝缘层。

3. 发明授权

US08824236B2 Memory access control device and manufacturing method 有权
标题翻译：存储器访问控制装置及其制造方法
公开(公告)号：US08824236B2
公开(公告)日：2014-09-02
申请号：US13811482
申请日：2012-02-21
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： G11C8/00 , G06F13/00 , G11C8/04 , G11C29/00
CPC分类号： G11C8/04 , G06F13/00 , G11C29/00 , G11C29/022 , G11C29/4401 , G11C29/822 , H01L2224/16225
摘要： A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.
摘要翻译：一种存储器访问控制装置，包括：比特位置信息存储单元，存储指示预定长度的比特序列中的一个或多个比特位置的比特位置信息; 读取单元，被配置为尝试从由逻辑地址接收单元接收的逻辑地址指定的范围内读取比特序列，从而以预定长度为单位从外部存储器接收第一比特序列，第一比特序列被组合的位数大于存储在由逻辑地址指定的范围内的位数; 比特序列提取单元，被配置为以由所述比特位置信息指定的所述一个或多个比特位置以所述预定长度为单位从所述第一比特序列提取一个或多个比特序列。

4. 发明授权

US08566762B2 Three-dimensional integrated circuit design device, three-dimensional integrated circuit design, method, and program 有权
标题翻译：三维集成电路设计器件，三维集成电路设计，方法和程序
公开(公告)号：US08566762B2
公开(公告)日：2013-10-22
申请号：US13637818
申请日：2012-02-17
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： G06F17/50
CPC分类号： H01L27/0211 , G06F17/505 , H01L27/0688
摘要： A worst-case temperature calculation unit calculates, based on heat value information of each layer of a three-dimensional integrated circuit to be designed and stack structure information of the three-dimensional integrated circuit, a worst-case temperature of a layer during operation that is targeted for logic synthesis. A logic synthesis library selection unit selects a library appropriate for the calculated worst-case temperature. A logic synthesis unit performs logic synthesis on the targeted layer with use of the selected library.
摘要翻译：最坏情况温度计算单元基于要设计的三维集成电路的每层的热值信息和三维集成电路的堆叠结构信息来计算操作期间的层的最坏情况温度，是逻辑综合的目标。逻辑合成库选择单元选择适合于计算的最坏情况温度的库。逻辑合成单元使用所选择的库来对目标层执行逻辑合成。

5. 发明申请

US20130121093A1 MEMORY ACCESS CONTROL DEVICE AND MANUFACTURING METHOD 有权
标题翻译：存储器访问控制装置和制造方法
公开(公告)号：US20130121093A1
公开(公告)日：2013-05-16
申请号：US13811482
申请日：2012-02-21
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： G11C8/04
CPC分类号： G11C8/04 , G06F13/00 , G11C29/00 , G11C29/022 , G11C29/4401 , G11C29/822 , H01L2224/16225
摘要： A memory access control device including: a bit position information storage unit storing bit position information indicating one or more bit positions in a bit sequence of a predetermined length; a reading unit configured to attempt to read a bit sequence from the range specified by the logical address received by the logical address receiving unit, thereby receiving a first bit sequence from the external memory in units of the predetermined length, the first bit sequence being composed of bits that are larger in number than bits stored in the range specified by the logical address; a bit sequence extracting unit configured to extract one or more bit sequences from the first bit sequence at the one or more bit positions indicated by the bit position information in units of the predetermined length.
摘要翻译：一种存储器访问控制装置，包括：比特位置信息存储单元，存储指示预定长度的比特序列中的一个或多个比特位置的比特位置信息; 读取单元，被配置为尝试从由逻辑地址接收单元接收的逻辑地址指定的范围内读取比特序列，从而以预定长度为单位从外部存储器接收第一比特序列，第一比特序列被组合的位数大于存储在由逻辑地址指定的范围内的位数; 比特序列提取单元，被配置为以由所述比特位置信息指定的所述一个或多个比特位置以所述预定长度为单位从所述第一比特序列提取一个或多个比特序列。

6. 发明授权

US08952499B2 Integrated circuit 有权
标题翻译：集成电路
公开(公告)号：US08952499B2
公开(公告)日：2015-02-10
申请号：US13641266
申请日：2011-10-26
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： H01L27/06 , H01L23/34 , H01L29/78 , H01L23/522
CPC分类号： H01L27/0629 , H01L23/345 , H01L23/5228 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a substrate, an electrode, two diffusion areas, and a resistance heater. The substrate includes a first surface and second surface that are substantially parallel to each other. The electrode is laminated onto the first surface. The two diffusion areas are disposed within the substrate in the vicinity of the electrode to form one transistor with the electrode. The resistance heater is located on an area of the second surface across the substrate from the electrode. The resistance heater produces heat by allowing electric current to flow.
摘要翻译：集成电路设置有基板，电极，两个扩散区域和电阻加热器。基板包括基本上彼此平行的第一表面和第二表面。电极层压到第一表面上。两个扩散区域设置在电极附近的衬底内，以形成具有电极的一个晶体管。电阻加热器位于从电极穿过基板的第二表面的区域上。电阻加热器通过允许电流流动来产生热量。

7. 发明申请

US20120304142A1 DESIGN SUPPORT DEVICE OF THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD THEREOF 有权
标题翻译：三维集成电路的设计支持设备及其方法
公开(公告)号：US20120304142A1
公开(公告)日：2012-11-29
申请号：US13576515
申请日：2011-11-10
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5045 , G06F17/5068 , H01L21/76898 , H01L24/16 , H01L24/32 , H01L25/0657 , H01L27/0688 , H01L2224/13025 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/2919 , H01L2224/32146 , H01L2224/32225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/14 , H01L2924/15311 , H01L2924/00
摘要： To provide a design support device of a three-dimensional integrated circuit capable of, in the case where a placement position of a through-via changes in the design phase of a three-dimensional integrated circuit composed of a plurality of semiconductor chips in layers, avoiding change of respective placement positions of other parts as much as possible. A design support device 400 includes a TSV placement unit 437 that determines respective placement positions of through-vias on one semiconductor chip, the through-bias each penetrating to connect to another semiconductor chip, a TSV reserved cell placement unit 439 that determines, based on the respective placement positions of the through-vias, respective placement positions of reserved cells as respective spare placement positions of the through-vias, and a mask data generation unit 445 that generates layout data that includes the respective placement positions of the through-vias and the respective placement positions of the reserved cells.
摘要翻译：为了提供一种三维集成电路的设计支持装置，其能够在贯通通孔的放置位置在层叠由多个半导体芯片组成的三维集成电路的设计阶段中变化的情况下，避免尽可能多地改变其他部分的各个放置位置。设计支持装置400包括TSV放置单元437，TSV放置单元437确定一个半导体芯片上的通孔的各个放置位置，每个穿透连接到另一个半导体芯片的通过偏压，TSV保留单元放置单元439，其基于通孔的相应放置位置，保留单元的相应放置位置作为通孔的相应备用布置位置，以及生成布局数据的掩模数据生成单元445，该布局数据包括贯通孔的各个放置位置，保留单元的相应放置位置。

8. 发明申请

US20130135004A1 THREE-DIMENSIONAL INTEGRATED CIRCUIT AND TESTING METHOD FOR THE SAME 有权
公开(公告)号：US20130135004A1
公开(公告)日：2013-05-30
申请号：US13642673
申请日：2012-06-04
申请人： Takashi Hashimoto , Takashi Morimoto
发明人： Takashi Hashimoto , Takashi Morimoto
IPC分类号： G01R31/28
CPC分类号： G01R31/2887 , G01R31/2801 , G01R31/2853 , G01R31/2889 , G01R31/318513 , H01L22/10 , H01L22/14 , H01L25/0657 , H01L2224/06181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.

9. 发明申请

US20130033303A1 INTEGRATED CIRCUIT 有权
标题翻译：集成电路
公开(公告)号：US20130033303A1
公开(公告)日：2013-02-07
申请号：US13641266
申请日：2011-10-26
申请人： Takashi Morimoto , Takashi Hashimoto
发明人： Takashi Morimoto , Takashi Hashimoto
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L23/345 , H01L23/5228 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit is provided with a substrate, an electrode, two diffusion areas, and a resistance heater. The substrate includes a first surface and second surface that are substantially parallel to each other. The electrode is laminated onto the first surface. The two diffusion areas are disposed within the substrate in the vicinity of the electrode to form one transistor with the electrode. The resistance heater is located on an area of the second surface across the substrate from the electrode. The resistance heater produces heat by allowing electric current to flow.
摘要翻译：集成电路设置有基板，电极，两个扩散区域和电阻加热器。基板包括基本上彼此平行的第一表面和第二表面。电极层压到第一表面上。两个扩散区域设置在电极附近的衬底内，以形成具有电极的一个晶体管。电阻加热器位于从电极穿过基板的第二表面的区域上。电阻加热器通过允许电流流动来产生热量。

10. 发明授权

US09121894B2 Three-dimensional integrated circuit and testing method for the same 有权
标题翻译：三维集成电路和测试方法相同
公开(公告)号：US09121894B2
公开(公告)日：2015-09-01
申请号：US13642673
申请日：2012-06-04
申请人： Takashi Hashimoto , Takashi Morimoto
发明人： Takashi Hashimoto , Takashi Morimoto
IPC分类号： G01R31/28 , G01R31/3185 , H01L25/065 , H01L21/66
CPC分类号： G01R31/2887 , G01R31/2801 , G01R31/2853 , G01R31/2889 , G01R31/318513 , H01L22/10 , H01L22/14 , H01L25/0657 , H01L2224/06181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.
摘要翻译：三维电路中的每个芯片包括一对连接，测试信号产生电路和测试结果判断电路。连接件与相邻的芯片电连接。测试信号产生电路向其中一个连接输出测试信号。测试结果判断电路从另一个连接接收信号，并从信号的状态检测信号的传输路径的导通状态。在分层芯片之前，导体将连接件连接起来形成串联连接，并且从串联连接的导通状态检测每个连接的导通状态。芯片分层后，一个芯片中的测试信号产生电路输出一个测试信号，另一个芯片中的测试结果判断电路接收测试信号，从而测试芯片之间连接的导通状态。

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