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    • 1. 发明申请
    • MULTIPLEXING CONTROL UNIT
    • 多路复用控制单元
    • US20100104013A1
    • 2010-04-29
    • US12578610
    • 2009-10-14
    • Takashi MATSUMOTOTakayuki SUZUKI
    • Takashi MATSUMOTOTakayuki SUZUKI
    • H04N11/02
    • H04N21/2368H04N21/41407H04N21/4341H04N21/44004
    • Provided is a multiplexing control unit operable to execute multiplex (MUX) and demultiplex (DEMUX), and enhanced in its processing performance. The multiplexing control unit includes a transport stream (TS) buffer, a multiplex-processing part, a video buffer and an audio buffer. When supplied with coded video and audio data from video and audio buffers, the multiplex-processing part conducts MUX, and on the other executes DEMUX on TS data stored in the TS buffer thereby to produce coded video and audio data. MUX and DEMUX processes by the multiplex-processing part are executed in sets of more than one frame processed according to moving-picture compression coding. Before start of execution of the process, whether or not the requirement of preparation for the execution is satisfied is judged inside the device, in which the judgment is made by checking storing states of the buffers.
    • 提供了一种可操作以执行多路复用(MUX)和解复用(DEMUX)并且增强其处理性能的多路复用控制单元。 复用控制单元包括传输流(TS)缓冲器,多路复用处理部分,视频缓冲器和音频缓冲器。 当从视频和音频缓冲器提供编码的视频和音频数据时,多路复用处理部分进行MUX,另一方面对存储在TS缓冲器中的TS数据执行DEMUX,从而产生编码的视频和音频数据。 通过多路复用处理部分的MUX和DEMUX处理以根据运动图像压缩编码处理的多于一帧的集合执行。 在开始执行处理之前,判断是否满足准备执行的要求,通过检查缓冲器的存储状态进行判断。
    • 2. 发明申请
    • DATA PROCESSING SYSTEM
    • 数据处理系统
    • US20110119465A1
    • 2011-05-19
    • US12946364
    • 2010-11-15
    • Takayuki SUZUKINobuaki KohinataTakashi Matsumoto
    • Takayuki SUZUKINobuaki KohinataTakashi Matsumoto
    • G06F12/02
    • G06F9/5016
    • The data processing system including: a memory block; a data-processing control block; a demultiplex-processing block; a multiplex-processing block; a decode-processing block; and an encode-processing block. In the system, the demultiplex-processing block, multiplex-processing block, decode-processing block, and encode-processing block each execute a process using memory regions in the memory block. During the execution, the data-processing control block changes a memory region to assign to the processing in response to a processing request based on results of processing which the block concerned executed in response to the preceding processing request. With the data processing system, a memory region can be used effectively even if a memory region size required for processing cannot be determined in advance.
    • 该数据处理系统包括:一个存储块; 数据处理控制块; 解复用处理块; 多路复用处理块; 解码处理块; 和编码处理块。 在该系统中,解复用处理块,多路复用处理块,解码处理块和编码处理块都使用存储器块中的存储区执行处理。 在执行期间,数据处理控制块根据处理结果响应于处理请求而改变存储区域以分配处理,该处理结果响应于先前的处理请求而执行。 利用数据处理系统,即使不能预先确定处理所需的存储器区域大小,也可以有效地使用存储区域。
    • 9. 发明申请
    • ANALYZER
    • 分析仪
    • US20110289374A1
    • 2011-11-24
    • US13110321
    • 2011-05-18
    • Takayuki SUZUKIShinjirou KIYONORyuji CHIBA
    • Takayuki SUZUKIShinjirou KIYONORyuji CHIBA
    • G06F11/00
    • G01N35/00732G01N2035/00811
    • An analyzer may include a body housing having a first ID, a first measurement module having a second ID that is different from the first ID, the first measurement module being releasably attachable to the body housing, a first memory in the body housing, the first memory being configured to store the first ID, first setting data and first correction data, a second memory in the first measurement module, the second memory being configured to store the second ID, second setting data and second correction data, a first CPU in the body housing, the first CPU being configured to detect the first measurement module having the second ID, and a first data transmission unit in the body housing, the first data transmission unit being configured to transmit the first setting data and the first correction data to the second memory.
    • 分析器可以包括具有第一ID的主体壳体,具有与第一ID不同的第二ID的第一测量模块,第一测量模块可释放地附接到主体壳体,主体壳体中的第一存储器,第一测量模块 存储器被配置为存储第一ID,第一设置数据和第一校正数据,第一测量模块中的第二存储器,第二存储器被配置为存储第二ID,第二设置数据和第二校正数据,第一CPU在 所述第一CPU被配置为检测具有所述第二ID的所述第一测量模块以及所述主体外壳中的第一数据传输单元,所述第一数据传输单元被配置为将所述第一设置数据和所述第一校正数据发送到所述主体外壳, 第二个记忆