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    • 4. 发明申请
    • SEMICONDUCTOR STORAGE DEVICE
    • 半导体存储设备
    • US20120243326A1
    • 2012-09-27
    • US13403294
    • 2012-02-23
    • Takashi MAEDA
    • Takashi MAEDA
    • G11C16/26
    • G11C16/26
    • According to one embodiment, a device includes transistors each with a path connected to a bit line, and circuits each includes a switch, the circuit being connected to the bit line. The device includes a amplifier connected to the transistor and to the circuit, and a latch connected to the amplifier to hold first data before read is carried out on a cell and to hold second data if a current equal to or a larger than a predetermined value flows via the bit line. In the device, the switch is turned on or off depending on data held in another latch located adjacently in a direction of the word lines, to control a connection between the bit line and connected to another bit line the amplifier via the circuit.
    • 根据一个实施例,一种器件包括各自具有连接到位线的路径的晶体管,并且电路各自包括开关,该电路连接到位线。 该装置包括连接到晶体管和电路的放大器,以及连接到放大器的锁存器,用于在小区上执行读取之前保存第一数据,并且如果电流等于或大于预定值,则保持第二数据 通过位线流动。 在该装置中,取决于保持在与字线方向相邻的另一个锁存器中的数据,开关被接通或断开,以控制位线之间的连接,并通过该电路连接到放大器的另一位线。
    • 6. 发明申请
    • NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE
    • 非挥发性半导体存储器件
    • US20110063916A1
    • 2011-03-17
    • US12727827
    • 2010-03-19
    • Takashi MAEDA
    • Takashi MAEDA
    • G11C16/02
    • G11C16/04H01L27/11556H01L27/11578
    • At least some of the memory transistors included in a first memory string are commonly connected to first conductive layers that are connected to at least some of the memory transistors included in a second memory string connected to the same third and fourth conductive layers as the first memory string. At least one of either the memory transistors or the back-gate transistor in the first memory string and at least one of either the memory transistors or the back-gate transistor in the second memory string are connected to the independent first or fifth conductive layers, respectively.
    • 包括在第一存储器串中的至少一些存储晶体管共同连接到第一导电层,其连接到连接到与第一存储器相同的第三和第四导电层的第二存储器串中的至少一些存储晶体管 串。 第一存储器串中的存储晶体管或背栅晶体管中的至少一个以及第二存储器串中的存储晶体管或背栅晶体管中的至少一个连接到独立的第一或第五导电层, 分别。
    • 8. 发明申请
    • NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20120243314A1
    • 2012-09-27
    • US13301948
    • 2011-11-22
    • Takashi MAEDA
    • Takashi MAEDA
    • G11C16/04H01L29/792
    • H01L27/11582H01L27/11565
    • A nonvolatile semiconductor memory device according to one aspect includes a semiconductor substrate, a memory string, a plurality of first conductive layers, a second conductive layer, and a third conductive layer. The memory string has a plurality of memory cells, a dummy transistor and a back gate transistor connected in series in a direction perpendicular to the semiconductor substrate. The plurality of first conductive layers are electrically connected to gates of the memory cells. The second conductive layer is electrically connected to a gate of the dummy transistor. The third conductive layer is electrically connected to a gate of the back gate transistor. The second conductive layer is short-circuited with the third conductive layer.
    • 根据一个方面的非易失性半导体存储器件包括半导体衬底,存储器串,多个第一导电层,第二导电层和第三导电层。 存储器串具有与垂直于半导体衬底的方向串联连接的多个存储单元,虚拟晶体管和背栅晶体管。 多个第一导电层电连接到存储单元的栅极。 第二导电层电连接到虚拟晶体管的栅极。 第三导电层电连接到背栅晶体管的栅极。 第二导电层与第三导电层短路。
    • 9. 发明申请
    • NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20120176836A1
    • 2012-07-12
    • US13091589
    • 2011-04-21
    • Natsuki IGUCHITakashi MAEDA
    • Natsuki IGUCHITakashi MAEDA
    • G11C16/28G11C16/04
    • G11C16/0483G11C16/10H01L27/1157H01L27/11573H01L27/11575H01L27/11582H01L29/7926
    • According to one embodiment, a non-volatile semiconductor memory device comprises memory strings. Each memory string comprises a semiconductor layer, control gates, a first selection gate, and a second selection gate. A semiconductor layer comprises a pair of pillar portions which extend in a vertical direction to a substrate, and a coupling portion formed to couple the pair of pillar portions. Control gates orthogonally intersect one of the pair of pillar portions or the other of the pair of pillar portions. A first selection gate orthogonally intersects one of the pair of pillar portions and is formed above the control gates. A second selection gate orthogonally intersects the other of the pair of pillar portions, is formed above the control gates, and is on the same level as the first selection gate as well as integrated with the first selection gate.
    • 根据一个实施例,非易失性半导体存储器件包括存储器串。 每个存储器串包括半导体层,控制栅极,第一选择栅极和第二选择栅极。 半导体层包括在垂直方向上延伸到基板的一对柱部分和形成为耦合所述一对柱部分的联接部分。 控制栅极与一对柱部分中的一个或一对柱部分中的另一个正交相交。 第一选择栅极与一对柱部分中的一个正交相交并形成在控制栅极的上方。 与控制栅极之间形成与第一选择栅极相同的第二选择栅极,与第一选择栅极集成,与第一选择栅极成一体。