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    • 1. 发明授权
    • Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program
    • 模拟半导体集成电路电源电压分配的方法和仿真程序
    • US07367000B2
    • 2008-04-29
    • US11305184
    • 2005-12-19
    • Takashi KuriharaKenji WadaMasahiro SuzukiEiji Fujine
    • Takashi KuriharaKenji WadaMasahiro SuzukiEiji Fujine
    • G06F17/50
    • G06F17/5036
    • The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven distribution of a floor plan taken into account. In Step S1, design information (Core size CS, core ring width CW, block shape BS, macro shape MS, block current BI, macro current MI, etc.) is inputted into a simulator. In Step S2, information regarding a floor plan (Block position BP, macro position MP, power I/O position IOP) is inputted into the simulator by a designer. In Step S3, the power unit management table is initialized, and resistance modeling and current source modeling are also carried out. In Step S5 (FIG. 1), the static IR drop is calculated based on the power unit management table CT obtained in Step S4.
    • 本发明的目的是提供一种用于模拟半导体集成电路的电源电压分布的方法,通过该方法可以尝试缩短制备功率单元模型所需的时间,并且可以执行高精度的仿真 考虑到平面布置的不均匀分布。 在步骤S1中,向模拟器输入设计信息(核心尺寸CS,核心环宽度CW,块形状BS,宏形状MS,块电流BI,宏观电流MI等)。 在步骤S2中,由设计者将关于平面图(块位置BP,宏位置MP,电力I / O位置IOP)的信息输入到模拟器。 在步骤S3中,对功率单元管理表进行初始化,并进行电阻建模和电流源建模。 在步骤S5(图1)中,基于在步骤S 4中获得的功率单元管理表CT计算静态IR下降。
    • 2. 发明申请
    • Method for simulating power voltage distribution of semiconductor integrated circuit and simulation program
    • 模拟半导体集成电路电源电压分配的方法和仿真程序
    • US20070044047A1
    • 2007-02-22
    • US11305184
    • 2005-12-19
    • Takashi KuriharaKenji WadaMasahiro SuzukiEiji Fujine
    • Takashi KuriharaKenji WadaMasahiro SuzukiEiji Fujine
    • G06F17/50
    • G06F17/5036
    • The invention has an object to provide a method for simulating power voltage distribution of a semiconductor integrated circuit, by which it is possible to attempt to shorten the time required for preparing a power unit model and it is possible to carry out a highly accurate simulation with uneven distribution of a floor plan taken into account. In Step S1, design information (Core size CS, core ring width CW, block shape BS, macro shape MS, block current BI, macro current MI, etc.) is inputted into a simulator. In Step S2, information regarding a floor plan (Block position BP, macro position MP, power I/O position IOP) is inputted into the simulator by a designer. In Step S3, the power unit management table is initialized, and resistance modeling and current source modeling are also carried out. In Step S5 (FIG. 1), the static IR drop is calculated based on the power unit management table CT obtained in Step S4.
    • 本发明的目的是提供一种用于模拟半导体集成电路的电源电压分布的方法,通过该方法可以尝试缩短制备功率单元模型所需的时间,并且可以执行高精度的仿真 考虑到平面布置的不均匀分布。 在步骤S1中,向模拟器输入设计信息(核心尺寸CS,核心环宽度CW,块形状BS,宏形状MS,块电流BI,宏观电流MI等)。 在步骤S2中,由设计者将关于平面图(块位置BP,宏位置MP,电力I / O位置IOP)的信息输入到模拟器。 在步骤S3中,对功率单元管理表进行初始化,并进行电阻建模和电流源建模。 在步骤S5(图1)中,基于在步骤S 4中获得的功率单元管理表CT计算静态IR下降。
    • 6. 发明授权
    • Input device for capacitive touch panel, input method and assembly
    • 电容式触摸屏输入装置,输入法和装配
    • US09134863B2
    • 2015-09-15
    • US13882941
    • 2011-09-05
    • Kenji ShinozakiMasahiro Suzuki
    • Kenji ShinozakiMasahiro Suzuki
    • G06F3/044G06F3/01G06F3/0354G06F3/039
    • G06F3/044G06F3/014G06F3/03545G06F3/039G06F2203/0331
    • Disclosed is an input device for a capacitive touch panel, which is an input device for inputting the position on the touch panel by making the input device contact with the touch panel, including an insulating layer (11) having flexibility and optical permeability, and a conductive layer (12) having optical permeability and laminated onto the insulating layer (11), and the input device (10) is integrally formed into a cylindrical shape so that the insulating layer (11) and the conductive layer (12) become a portion to be contacted with the touch panel. Thereby, users less likely to have a sense of wear and tear of fingers, the position pointed by the input device on the touch panel is precisely recognized with ease, the accuracy of the position detected by the touch panel is improved, and input means is less likely to be lost though the input device is lost.
    • 公开了一种用于电容式触摸屏的输入装置,其是通过使输入装置与触摸面板接触来输入触摸面板上的位置的输入装置,包括具有柔性和透光性的绝缘层(11),以及 具有光导率并层压在绝缘层(11)上的导电层(12),并且输入装置(10)一体地形成为圆柱形状,使得绝缘层(11)和导电层(12)成为一部分 与触摸面板接触。 因此,用户不太可能具有手指的磨损感,触摸面板上的输入装置指向的位置被容易地识别,提高了触摸面板检测到的位置的精度,并且输入装置是 丢失输入设备的可能性较小。
    • 9. 发明授权
    • Solid electrolytic capacitor element, method for manufacturing same, and jig for manufacturing same
    • 固体电解电容器元件及其制造方法及其制造用夹具
    • US08847437B2
    • 2014-09-30
    • US13257153
    • 2010-03-16
    • Kazumi NaitoMasahiro Suzuki
    • Kazumi NaitoMasahiro Suzuki
    • H02M3/06
    • H01G9/0032C09D5/4476C25D13/04C25D13/20C25D13/22H01G9/0036H01G9/07H01G9/15Y10T29/417
    • Provided is a jig for manufacturing electrolytic capacitor elements wherein the jig is for forming dielectric layers on the surfaces of anode bodies by anodic oxidation or for forming semiconductor layers on the dielectric layers formed on the surfaces of the anode bodies. The jig for manufacturing the electrolytic capacitor elements comprises (i) a plurality of power supply circuits which are provided on an insulating substrate and to each of which a voltage-limiting value and a current-limiting value can be set, (ii) connection terminals for the anode bodies which are electrically connected to the respective outputs of the power supply circuits, and (iii) a terminal for setting the voltage-limiting values to the power supply circuits and a terminal for setting the current-limiting values to the power supply circuits; in the jig, a proper current can be set corresponding to the progress of the anodic oxidation and electrolytic polymerization. A method for manufacturing the electrolytic capacitor elements using the jig.
    • 提供一种用于制造电解电容器元件的夹具,其中夹具用于通过阳极氧化在阳极体的表面上形成介电层,或用于在形成在阳极体的表面上的电介质层上形成半导体层。 用于制造电解电容器元件的夹具包括:(i)设置在绝缘基板上的多个电源电路,并且每个电源电路可以设置电压限制值和限流值,(ii)连接端子 对于与电源电路的各个输出电连接的阳极体,以及(iii)用于将电压限制值设定到电源电路的端子和用于将电流限制值设定为电源的端子 电路; 在夹具中,可以根据阳极氧化和电解聚合的进行设定适当的电流。 一种使用夹具制造电解电容器元件的方法。