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    • 5. 发明授权
    • Timing phase control apparatus and timing phase control method
    • 定时相位控制装置和定时相位控制方法
    • US6002712A
    • 1999-12-14
    • US898493
    • 1997-07-22
    • Takashi KakuNoboru KawadaHideo Miyazawa
    • Takashi KakuNoboru KawadaHideo Miyazawa
    • H03H17/02H03H17/08H04B3/06H04L7/02H04L27/22H04B1/38H03K5/159
    • H04L7/0029H04L7/0087H04L7/007
    • The present invention discloses a timing phase control apparatus which is particularly suitable for use in a modem used for very high speed data transmission employing a metallic line. The timing phase control apparatus includes a timing phase extracting portion to extract timing phase information from an input signal, a timing phase control filter portion to make a timing phase control to the input signal depending upon the timing phase information from the timing phase extracting portion through filter processing using a coefficient operation having a preset impulse response characteristic, and a filter processing coefficient determining portion to determine a coefficient used for the filter processing in the timing phase control filter portion depending upon the timing phase information and information about an approximate expression of the impulse response characteristic. An accuracy of a tap coefficient can be improved while reducing an amount of information about the tap coefficient, which should be stored.
    • 本发明公开了一种定时相位控制装置,其特别适用于采用金属线路进行超高速数据传输的调制解调器。 定时相位控制装置包括定时相位提取部分,用于从输入信号提取定时相位信息;定时相位控制滤波器部分,用于根据来自定时相位提取部分的定时相位信息对输入信号进行定时相位控制, 使用具有预设脉冲响应特性的系数操作的滤波处理和滤波处理系数确定部分,以根据定时相位信息确定用于定时相位控制滤波器部分中的滤波处理的系数,以及关于近似表达式的信息 脉冲响应特性。 可以减少抽头系数的精度,同时减少应该存储的抽头系数的信息量。
    • 6. 发明授权
    • Phase jitter extraction circuit and phase jitter cancellation circuit
    • 相位抖动提取电路和相位抖动消除电路
    • US5719907A
    • 1998-02-17
    • US534161
    • 1995-09-26
    • Takashi KakuHideo Miyazawa
    • Takashi KakuHideo Miyazawa
    • H04B3/04H04B3/06H04L1/20H04L25/02H04L25/08H04L27/22H04L27/38H04L25/38H04L5/16
    • H04L27/3872H04L1/205
    • The invention provides a phase jitter extraction circuit and a phase jitter cancellation circuit for use with a reception section of a communication apparatus such as a modem used to transmit data using a telephone line or a private line, which are improved in that noise of a signal is prevented from increasing to suppress phase jitters with a high degree of accuracy and high noise components can be suppressed irrespective of the power of the input signal. The phase jitter extraction circuit includes a phase jitter detection section for detecting phase jitters from input/output information of a signal discriminator, a phase jitter forecasting section for forecasting phase jitters which will be produced later from the phase jitters detected by the phase jitter detection section, a selector for selectively outputting the phase jitters detected by the phase jitter detection section or the forecast phase jitters obtained by the phase jitter forecasting section, and a selector control section for discriminating a region of signal points received by the communication apparatus by way of a transmission line and controlling the selector in accordance with a result of the discrimination.
    • 本发明提供一种相位抖动提取电路和相位抖动消除电路,用于与诸如调制解调器之类的通信装置的接收部分一起使用,该调制解调器用于使用电话线路或专用线路传输数据, 防止增加以高精度抑制相位抖动,并且与输入信号的功率无关,可以抑制高噪声分量。 相位抖动提取电路包括:相位抖动检测部分,用于从信号鉴别器的输入/输出信息中检测相位抖动;相位抖动预测部分,用于预测稍后将由相位抖动检测部分检测的相位抖动产生的相位抖动; 选择器,用于选择性地输出由相位抖动检测部分检测的相位抖动或由相位抖动预测部分获得的预测相位抖动,以及选择器控制部分,用于通过通信装置接收的信号点的区域 传输线,并根据鉴别结果控制选择器。
    • 7. 发明授权
    • Modulator and demodulator apparatus as well as modulation and
demodulation method
    • 调制器和解调器装置以及调制和解调方法
    • US5559799A
    • 1996-09-24
    • US108536
    • 1993-08-19
    • Hiroyasu MurataHideo MiyazawaTakashi Kaku
    • Hiroyasu MurataHideo MiyazawaTakashi Kaku
    • H04L27/00H04L5/06H04L27/22H04L27/233H04L27/38H04B1/38H04J1/14
    • H04L5/06H04L27/2338
    • A modulator and demodulator apparatus for use with a network is provided. The modulator and demodulator apparatus comprises a modulation section which includes a timing phase discrimination section for receiving, as an input signal thereto, a demodulation vector signal sampled into a digital value and discriminating to which one of a plurality of regions of a discrimination plane the phase of the input signal belongs. The timing phase discrimination section supplies, as an input to a next processing stage, a rotation vector obtained by rotating an input vector, moves the rotation vector to a quadrant which includes a reference discrimination region of the discrimination plane and performs, when the vector after the movement is not in the reference discrimination region, a predetermined calculation. When the vector after the movement comes to the reference discrimination region, another calculation is performed. This discriminates a timing phase of the input vector from the result of the calculation.
    • 提供一种用于网络的调制器和解调器装置。 调制器和解调器装置包括调制部分,其包括定时相位鉴别部分,用于将采样成数字值的解调矢量信号作为输入信号,并将鉴别面的多个区域中的哪一个区分为相位 的输入信号属于。 定时相位识别部将作为输入向下一个处理级的输入提供通过旋转输入矢量而获得的旋转矢量,将旋转矢量移动到包括鉴别面的参考识别区域的象限,并且当后向量 运动不在参考识别区域中,所以是预定的计算。 当运动之后的矢量进入参考识别区域时,进行另一次计算。 这样就从计算结果中辨别出输入向量的定时相位。
    • 9. 发明授权
    • PLL circuit
    • PLL电路
    • US06377647B1
    • 2002-04-23
    • US09205804
    • 1998-12-04
    • Takashi KakuNoboru KawadaHideo Miyazawa
    • Takashi KakuNoboru KawadaHideo Miyazawa
    • H03D324
    • H03L7/091H04L7/0331
    • A PLL circuit that causes an internal oscillation signal to lock to an external input clock signal, and is capable of suppressing jitter. The PLL circuit includes a frequency dividing circuit for frequency-dividing an input clock signal; a voltage-controlled oscillator; a missing-pulse clock signal creation circuit for creating, based on an output signal of the voltage-controlled oscillator, a missing-pulse clock signal having a higher speed than that of an output signal of the frequency dividing circuit and having a periodic missing-pulse portion; a phase comparator circuit for sampling the output signal of the frequency dividing circuit by using the missing-pulse clock signal; a shift register for storing a change in the output signal of the phase comparator circuit; and a digital signal processing circuit for converting a value stored in the shift register into a phase difference, and for controlling the input voltage to the voltage-controlled oscillator based on the phase difference.
    • PLL电路使内部振荡信号锁定到外部输入时钟信号,并且能够抑制抖动。 PLL电路包括用于对输入时钟信号进行分频的分频电路; 压控振荡器; 一个缺失脉冲时钟信号产生电路,用于根据压控振荡器的输出信号创建一个具有比分频电路的输出信号高的缺失脉冲时钟信号, 脉冲部分 相位比较器电路,用于通过使用缺失脉冲时钟信号对分频电路的输出信号进行采样; 移位寄存器,用于存储相位比较器电路的输出信号的变化; 以及数字信号处理电路,用于将存储在移位寄存器中的值转换为相位差,并且用于基于相位差控制到压控振荡器的输入电压。