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1. 发明授权

US5537437A Initialization equalization for modulation and demodulation using special training pattern 失效
标题翻译：使用特殊训练模式进行调制和解调的初始化均衡
公开(公告)号：US5537437A
公开(公告)日：1996-07-16
申请号：US505479
申请日：1995-07-21
申请人： Takashi Kaku , Hiroyasu Murata , Noboru Kawada , Kyoko Hirao , Hideo Miyazawa , Yuri Nigaki
发明人： Takashi Kaku , Hiroyasu Murata , Noboru Kawada , Kyoko Hirao , Hideo Miyazawa , Yuri Nigaki
IPC分类号： H04B3/10 , H04L7/04 , H04L27/01 , H04L27/22 , H03H7/30
CPC分类号： H04L7/041 , H04L7/046
摘要： A modulation and demodulation system suitable for use with a modem (modulator and demodulator apparatus) of a first polling type. The system allows reproduction of a signal necessary for initialization of a reception section of a modulator and demodulator apparatus with certainty in a short training time. The modulation and demodulation system is constructed such that, upon transmission of data, training data of a particular pattern are modulated and transmitted prior to transmission of the data, and such training data are demodulated by demodulation means and initialization of a reception section of the modulation and demodulation system is performed using the demodulation training data. The pattern of the training data to be transmitted includes an arrangement of signals wherein signals having phases different by 180.degree. from each other are arranged alternately, and a signal having the same phase as the last signal is arranged intermediately.
摘要翻译：适用于第一轮询类型的调制解调器（调制器和解调器装置）的调制和解调系统。该系统允许在短时间内确定地再现调制器和解调器装置的接收部分的初始化所需的信号。调制和解调系统被构造成使得在传输数据时，在传输数据之前对特定模式的训练数据进行调制和发送，并且这样的训练数据由解调装置解调并且调制的接收部分的初始化并且使用解调训练数据执行解调系统。要发送的训练数据的模式包括信号的布置，其中具有彼此相差180°的相位的信号交替布置，并且具有与最后信号相同相位的信号被布置在中间。

2. 发明授权

US5963593A Line equalizer control method, and integrating circuit, frequency shift circuit and transmission device 失效
标题翻译：线路均衡器控制方法，积分电路，频移电路和传输装置
公开(公告)号：US5963593A
公开(公告)日：1999-10-05
申请号：US825067
申请日：1997-03-27
申请人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa , Yuri Nigaki
发明人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa , Yuri Nigaki
IPC分类号： H03H17/00 , H04B3/04 , H04B3/10 , H03H7/40 , H03H5/00
CPC分类号： H04B3/04 , H04L25/03885
摘要： A method of controlling a line equalizer such as a modem includes an extracting step of extracting plural tone signals each superimposed on a transmission signal and having a specific frequency component; a judging step of judging levels of the extracted tone signals; and a controlling step of controlling characteristic of a line equalizer which equalizes a receive signal, based on the levels of the judged tone signals. A line equalizer is controlled without performing an exchange of a training signal prior to starting a data transmission and without increasing the amount of hardware of a modem or the like.
摘要翻译：一种控制诸如调制解调器之类的线路均衡器的方法包括一个提取步骤，提取叠加在传输信号上并具有特定频率分量的多个音调信号; 判断步骤，用于判断所提取的音调信号的电平; 以及控制步骤，基于所判断的音调信号的电平来控制均衡接收信号的线均衡器的特性。在开始数据传输之前不必执行训练信号的交换，而不增加调制解调器等的硬件量，可以控制线路均衡器。

3. 发明授权

US6078624A Judging method and a precoding apparatus 失效
标题翻译：判断方法和预编码装置
公开(公告)号：US6078624A
公开(公告)日：2000-06-20
申请号：US829065
申请日：1997-03-31
申请人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa , Yuri Nigaki
发明人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa , Yuri Nigaki
IPC分类号： H04L27/18 , H04L25/03 , H04L25/497 , H04L5/12 , H04L23/02
CPC分类号： H04L25/4975 , H04L25/03343 , H04L25/497
摘要： A preceding apparatus for calculating a difference between an inputted signal point and an output signal obtained one timing before and outputting the difference has a position information judging unit for judging which position on a vector plane the output signal obtained one timing before is located in, and a signal point selecting storage for outputting any signal point among a plurality of signal points generated correspondingly to a signal point inputted from the outside with a result of the judgement fed form the position information judging unit nd the signal point inputted from the outside as an address, thereby decreasing the number of cycles required by a DSP process and realizing a precoder process in a degree achieved hitherto.
摘要翻译：一种用于计算输入信号点和之前获得的一个定时之前的输出信号之间的差并输出该差的先前装置具有位置信息判断单元，用于判断向量平面上哪一个位置在一个定时获得的输出信号，以及信号点选择存储器，用于输出与从外部输入的信号点相对应地生成的多个信号点中的任何信号点，其中从位置信息判断单元输入的判断结果将从外部输入的信号点作为地址，从而减少了DSP处理所需的周期数，并实现了迄今为止所达到的程度的预编码器处理。

4. 发明授权

US6021160A Training method for non-nyquist transmission system and training data transmission apparatus for non-nyquist transmission system 失效
标题翻译：非尼奎斯特传输系统的训练方法和非尼奎斯特传输系统的训练数据传输装置
公开(公告)号：US6021160A
公开(公告)日：2000-02-01
申请号：US539067
申请日：1995-10-04
申请人： Takashi Kaku , Noboru Kawada , Yuri Nigaki
发明人： Takashi Kaku , Noboru Kawada , Yuri Nigaki
IPC分类号： H04L27/00 , H04B3/10 , H04L1/00 , H04L7/10 , H03H7/30
CPC分类号： H04L7/10 , H04L1/0078
摘要： The invention provides a training method for a non-Nyquist transmission system and a training data transmission apparatus for a non-Nyquist transmission system by which initialization processing of a reception section can be performed with certainty even where a non-Nyquist transmission system is employed. Prior to transmission of data in accordance with a non-Nyquist transmission system, training data having a first repeat signal portion formed from a group of signals including components of a lower rate than a Nyquist interval, a first multi-value random signal portion formed from multi-value random signals, a second repeat signal portion formed from a group of signals including components of a lower rate than the Nyquist interval, a third repeat signal portion formed from a group of signals which include components lower in rate than the Nyquist interval and wherein a first signal point is different by 180 degrees in phase from a first signal which forms the second repeat signal portion, and a second multi-value random signal portion formed from multi-value random signals, are transmitted from a transmission section. The training data are received by a reception section, and initialization processing of the reception section is performed using the received training data.
摘要翻译：本发明提供了一种用于非奈奎斯特传输系统的训练方法和用于非奈奎斯特传输系统的训练数据传输装置，通过该训练数据传输装置，即使采用非奈奎斯特传输系统，也可以确定地执行接收部分的初始化处理。在根据非奈奎斯特传输系统传输数据之前，具有第一重复信号部分的训练数据，该第一重复信号部分由包括比奈奎斯特（Nyquist）间隔较低的分量的信号组形成，第一多值随机信号部分由多值随机信号，由包括比奈奎斯特间隔较低的分量的信号组的一组信号形成的第二重复信号部分，由包括比奈奎斯特间隔更低的分量的一组信号形成的第三重复信号部分，以及其中第一信号点与形成第二重复信号部分的第一信号的相位相差180度，并且从多值随机信号形成的第二多值随机信号部分从发送部分发送。训练数据由接收部分接收，并且使用所接收的训练数据来执行接收部分的初始化处理。

5. 发明授权

US06377647B1 PLL circuit 失效
标题翻译： PLL电路
公开(公告)号：US06377647B1
公开(公告)日：2002-04-23
申请号：US09205804
申请日：1998-12-04
申请人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa
发明人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa
IPC分类号： H03D324
CPC分类号： H03L7/091 , H04L7/0331
摘要： A PLL circuit that causes an internal oscillation signal to lock to an external input clock signal, and is capable of suppressing jitter. The PLL circuit includes a frequency dividing circuit for frequency-dividing an input clock signal; a voltage-controlled oscillator; a missing-pulse clock signal creation circuit for creating, based on an output signal of the voltage-controlled oscillator, a missing-pulse clock signal having a higher speed than that of an output signal of the frequency dividing circuit and having a periodic missing-pulse portion; a phase comparator circuit for sampling the output signal of the frequency dividing circuit by using the missing-pulse clock signal; a shift register for storing a change in the output signal of the phase comparator circuit; and a digital signal processing circuit for converting a value stored in the shift register into a phase difference, and for controlling the input voltage to the voltage-controlled oscillator based on the phase difference.
摘要翻译： PLL电路使内部振荡信号锁定到外部输入时钟信号，并且能够抑制抖动。 PLL电路包括用于对输入时钟信号进行分频的分频电路; 压控振荡器; 一个缺失脉冲时钟信号产生电路，用于根据压控振荡器的输出信号创建一个具有比分频电路的输出信号高的缺失脉冲时钟信号，脉冲部分相位比较器电路，用于通过使用缺失脉冲时钟信号对分频电路的输出信号进行采样; 移位寄存器，用于存储相位比较器电路的输出信号的变化; 以及数字信号处理电路，用于将存储在移位寄存器中的值转换为相位差，并且用于基于相位差控制到压控振荡器的输入电压。

6. 发明授权

US5757865A Carrier phase control circuit 失效
标题翻译：载波相位控制电路
公开(公告)号：US5757865A
公开(公告)日：1998-05-26
申请号：US553990
申请日：1995-11-06
申请人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa
发明人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa
IPC分类号： H04L27/38 , H04L27/00 , H04L27/22 , H04L27/233 , H04L27/06
CPC分类号： H04L27/2332 , H04L2027/003 , H04L2027/0055
摘要： The invention provides a carrier phase control circuit which can eliminate a phase intercept fluctuation so that, when the carrier phase control circuit is applied to a very high speed modem having a communication speed of, for example, 28.8 kbps, occurrence of a communication error can be suppressed and the modem has an improved characteristic. The carrier phase control circuit is provided on a reception side of a communication apparatus and interposed between an automatic equalizer and a signal decision section. The carrier phase control circuit includes a frequency offset removal section for predicting and removing an offset of a frequency of a transmission signal based on an output of the automatic equalizer, and a phase intercept variation removal section for predicting and removing a phase intercept variation of the transmission signal based on an output of the frequency offset removal section and inputting a resulted signal as an output thereof to the signal decision section.
摘要翻译：本发明提供了一种载波相位控制电路，其可以消除相位截距波动，使得当载波相位控制电路被应用于具有例如28.8kbps的通信速度的非常高速的调制解调器时，可能发生通信错误被抑制，调制解调器具有改进的特性。载波相位控制电路设置在通信装置的接收侧，并插入在自动均衡器和信号判定部分之间。载波相位控制电路包括：频率偏移消除部分，用于基于自动均衡器的输出来预测和去除发送信号频率的偏移;相位截距变化去除部分，用于预测和去除发送信号的相位截距变化，基于频率偏移去除部的输出的发送信号，并将得到的信号作为其输出输入到信号判定部。

7. 发明授权

US6002712A Timing phase control apparatus and timing phase control method 失效
标题翻译：定时相位控制装置和定时相位控制方法
公开(公告)号：US6002712A
公开(公告)日：1999-12-14
申请号：US898493
申请日：1997-07-22
申请人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa
发明人： Takashi Kaku , Noboru Kawada , Hideo Miyazawa
IPC分类号： H03H17/02 , H03H17/08 , H04B3/06 , H04L7/02 , H04L27/22 , H04B1/38 , H03K5/159
CPC分类号： H04L7/0029 , H04L7/0087 , H04L7/007
摘要： The present invention discloses a timing phase control apparatus which is particularly suitable for use in a modem used for very high speed data transmission employing a metallic line. The timing phase control apparatus includes a timing phase extracting portion to extract timing phase information from an input signal, a timing phase control filter portion to make a timing phase control to the input signal depending upon the timing phase information from the timing phase extracting portion through filter processing using a coefficient operation having a preset impulse response characteristic, and a filter processing coefficient determining portion to determine a coefficient used for the filter processing in the timing phase control filter portion depending upon the timing phase information and information about an approximate expression of the impulse response characteristic. An accuracy of a tap coefficient can be improved while reducing an amount of information about the tap coefficient, which should be stored.
摘要翻译：本发明公开了一种定时相位控制装置，其特别适用于采用金属线路进行超高速数据传输的调制解调器。定时相位控制装置包括定时相位提取部分，用于从输入信号提取定时相位信息;定时相位控制滤波器部分，用于根据来自定时相位提取部分的定时相位信息对输入信号进行定时相位控制，使用具有预设脉冲响应特性的系数操作的滤波处理和滤波处理系数确定部分，以根据定时相位信息确定用于定时相位控制滤波器部分中的滤波处理的系数，以及关于近似表达式的信息脉冲响应特性。可以减少抽头系数的精度，同时减少应该存储的抽头系数的信息量。

8. 发明授权

US06448861B2 PLL controller, method of PLL control, and limiter 失效
标题翻译： PLL控制器，PLL控制方法和限幅器
公开(公告)号：US06448861B2
公开(公告)日：2002-09-10
申请号：US09788841
申请日：2001-02-20
申请人： Noboru Kawada , Takashi Kaku , Takeshi Asahina , Tohru Ogawa , Hideo Miyazawa
发明人： Noboru Kawada , Takashi Kaku , Takeshi Asahina , Tohru Ogawa , Hideo Miyazawa
IPC分类号： H03L706
CPC分类号： H03L7/091 , H03L7/093
摘要： A limiter is connected with the output of a PLL to limit the amplitude of the output from the PLL. The output from limiter is supplied to a voltage-controlled oscillator (VCXO). The limiter determines the difference between the input signal and the output signal. If the difference exceeds a predetermined value, the change in the output from the limiter is limited to the predetermined value. If the difference does not exceed the predetermined value, the change in the output is considered to be a difference value.
摘要翻译：限幅器与PLL的输出端相连以限制PLL输出的幅度。限幅器的输出被提供给压控振荡器（VCXO）。限幅器确定输入信号和输出信号之间的差异。如果差异超过预定值，则限制器的输出的变化被限制为预定值。如果该差异不超过预定值，则输出的变化被认为是差值。

9. 发明授权

US5388122A Modulation and demodulation system 失效
标题翻译：调制解调系统
公开(公告)号：US5388122A
公开(公告)日：1995-02-07
申请号：US109043
申请日：1993-08-19
申请人： Noboru Kawada , Yuri Nigaki
发明人： Noboru Kawada , Yuri Nigaki
IPC分类号： H04J1/00 , H04J1/14 , H04L5/06 , H04L7/00 , H04L27/00 , H04L27/233 , H04B1/38
CPC分类号： H04J1/14 , H04L27/2338 , H04L5/06 , H04L7/0083
摘要： A modulation and demodulation system which modulates and demodulates a signal in a main channel for main data and a secondary channel for secondary data obtained by frequency division and uses, upon demodulation, a frequency timing extracted from the secondary channel as a sampling timing for an analog to digital conversion device for the main channel. The modulation and demodulation system is improved in that it can rapidly restore, when a timing error occurs, a processing condition in which a normal timing is used, and comprises a demodulation device which includes a phase timing error detection device for detecting an error of phase timing information extracted from the main channel and a storage device for storing the phase timing information. When the phase timing error detection device detects the error of the phase timing information, the demodulation device performs demodulation processing of main data using the phase timing information stored in the storage device.
摘要翻译：调制和解调用于主数据的主信道中的信号和用于通过分频获得的二次数据的辅助信道的解调，并且在解调时使用从辅助信道提取的频率定时作为模拟的采样定时到主频道的数字转换设备。改进了调制和解调系统，当定时错误发生时，可以快速恢复其中使用正常定时的处理条件，并且包括解调装置，该解调装置包括用于检测相位误差的相位定时误差检测装置从主频道提取的定时信息和用于存储相位定时信息的存储装置。当相位定时误差检测装置检测到相位定时信息的误差时，解调装置使用存储在存储装置中的相位定时信息来执行主数据的解调处理。

10. 发明授权

US5563908A Modulator and demodulator apparatus 失效
标题翻译：调制器和解调器
公开(公告)号：US5563908A
公开(公告)日：1996-10-08
申请号：US472291
申请日：1995-06-07
申请人： Takashi Kaku , Noboru Kawada
发明人： Takashi Kaku , Noboru Kawada
IPC分类号： H04J1/00 , H04L27/00 , H04L27/22 , H04L27/233 , H04M11/06 , H04B1/38
CPC分类号： H04M11/06 , H04L27/22 , H04L27/2338
摘要： The invention provides a modulator and demodulator apparatus (modem) which modulates and demodulates a signal in a main channel, for main data, and a secondary channel, for secondary data obtained by frequency division, and which includes a carrier detection unit for detecting a carrier from a demodulation signal and executes a data processing sequence for the demodulation signal in accordance with a result of detection by the carrier detection unit. This apparatus can detect a carrier of a low roll-off ratio accurately and stably without a dispersion in detection time and, consequently, data of a demodulation signal can be processed with certainty. The modulator and demodulator apparatus comprises a filter having a characteristic wherein the time axis response is slow and it is provided at a stage preceding the carrier detection unit so that a demodulation signal which has passed through the filter is input to the carrier detection unit. The modulator and demodulator apparatus includes a modulation unit for modulating and transmitting data having a turnoff sequence with a last end and a demodulation unit for receiving and demodulating a receive signal to reproduce data. The modulation unit includes a tone signal generation unit for adding a tone signal to the last end of the turnoff sequence of the data to be transmitted.
摘要翻译：本发明提供了一种调制器和解调器装置（调制解调器），其对主数据的主信道中的信号和辅助信道进行调制和解调，用于通过分频获得的二次数据，并且包括用于检测载波的载波检测单元根据解调信号，根据载波检测单元的检测结果执行解调信号的数据处理顺序。该装置可以精确稳定地检测低滚降比的载波，而不会在检测时间内出现分散，从而可以确定地处理解调信号的数据。调制器和解调器装置包括具有时间轴响应慢的特性的滤波器，并且其被提供在载波检测单元之前的阶段，使得已经通过滤波器的解调信号被输入到载波检测单元。调制器和解调器装置包括用于调制和发送具有最后一端的切断序列的数据的调制单元和用于接收和解调接收信号以再现数据的解调单元。调制单元包括音调信号生成单元，用于将音调信号与要发送的数据的关闭序列的最后一个相加。

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