专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5500542A Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor 失效
公开(公告)号：US5500542A
公开(公告)日：1996-03-19
申请号：US194988
申请日：1994-02-14
申请人： Takashi Iida , Satoru Sumi , Hiroshi Shimizu , Akinori Tahara , Isao Amano , Tetsuya Nakajima
发明人： Takashi Iida , Satoru Sumi , Hiroshi Shimizu , Akinori Tahara , Isao Amano , Tetsuya Nakajima
IPC分类号： H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/118 , H01L27/10 , H01L23/62
CPC分类号： H01L27/0255 , H01L27/11803 , H01L2924/0002
摘要： Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

2. 发明授权

US5672895A Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor 失效
标题翻译：具有防静电保护电路的半导体集成电路及其布局设计方法
公开(公告)号：US5672895A
公开(公告)日：1997-09-30
申请号：US575030
申请日：1995-12-19
申请人： Takashi Iida , Satoru Sumi , Hiroshi Shimizu , Akinori Tahara , Isao Amano , Tetsuya Nakajima
发明人： Takashi Iida , Satoru Sumi , Hiroshi Shimizu , Akinori Tahara , Isao Amano , Tetsuya Nakajima
IPC分类号： H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04 , H01L27/118 , H01L27/01 , H01L23/62 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/0255 , H01L27/11803 , H01L2924/0002
摘要： Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.
摘要翻译：二极管行以与单元行的排列方向相同的方向以间隔L布置。每个二极管行具有一排pn结，每一个pn结形成在衬底上并且沿垂直于互连轨道的轨道布置。单元之间的互连将MOS晶体管的栅极自动连接到二极管，而不需要考虑哪个栅极应连接到二极管。在制造半导体集成电路的过程中，MOS晶体管的栅极和二极管之间的布线长度小于防止栅极氧化物的静电击穿的上限值。每个pn结可以形成在必要的输入信号线，必要的接地线，MOS晶体管的漏极的底部或者在宏单元之外的电源线下。

3. 发明授权

US6002155A Semiconductor integrated circuit with protection circuit against electrostatic breakdown and layout design method therefor 失效
标题翻译：具有防静电保护电路的半导体集成电路及其布局设计方法
公开(公告)号：US6002155A
公开(公告)日：1999-12-14
申请号：US874980
申请日：1997-06-13
申请人： Akinori Tahara , Isao Amano
发明人： Akinori Tahara , Isao Amano
IPC分类号： H01L27/02 , H01L27/118 , H01L23/62
CPC分类号： H01L27/11803 , H01L27/0255 , H01L2924/0002
摘要： Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.
摘要翻译：二极管行以与单元行的排列方向相同的方向以间隔L布置。每个二极管行具有一排pn结，每一个pn结形成在衬底上并且沿垂直于互连轨道的轨道布置。电池之间的互连自动将MOS晶体管的栅极连接到二极管，而不需要考虑哪个栅极应连接到二极管。在制造半导体集成电路的过程中，MOS晶体管的栅极和二极管之间的布线长度小于防止栅极氧化物的静电击穿的上限值。每个pn结可以形成在必要的输入信号线，必要的接地线，MOS晶体管的漏极的底部或者在宏单元之外的电源线下。

4. 发明授权

US06753574B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06753574B2
公开(公告)日：2004-06-22
申请号：US09815010
申请日：2001-03-23
申请人： Seiichiro Yamaguchi , Mitsuaki Kai , Isao Amano
发明人： Seiichiro Yamaguchi , Mitsuaki Kai , Isao Amano
IPC分类号： H01L2976
CPC分类号： H01L29/78615 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/78621 , H01L29/78645 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.
摘要翻译：半导体器件包括：导电层，包括：沟道区; 源极区域和漏极区域，夹着沟道区域; 以及与所述沟道区域连接且与所述源极区域和所述漏极区域相邻的主体区域; 形成在所述沟道区域之上的栅极电极，所述沟道区域之间插入栅极绝缘膜; 形成在至少所述漏极区域和所述体区域之间的界面附近的所述主体区域上并与所述栅电极电绝缘的虚拟电极; 以及形成在除了形成所述虚拟电极的区域之外的所述体区域中的体接触区域。栅电极和虚拟电极彼此电绝缘，由此具有主体接触的半导体器件可以使栅电容大大降低。因此，可以抑制晶体管的速度性能的劣化。

5. 发明授权

US06556901B2 Electronic control unit and method measuring and using electric power-off period 有权
公开(公告)号：US06556901B2
公开(公告)日：2003-04-29
申请号：US09874210
申请日：2001-06-06
申请人： Atsushi Sugimura , Isao Amano
发明人： Atsushi Sugimura , Isao Amano
IPC分类号： G06F700
CPC分类号： F02D41/222 , F01P11/16 , F01P2031/00 , F02D41/26
摘要： In an ECU for vehicles, a clock IC operates with sub power and measures time continuously irrespective of whether a microcomputer is operating. The microcomputer determines whether the clock IC has been reset on the basis of a history indicating that the sub power has fallen below a data holding voltage of an SRAM which also operates on the sub power. Alternatively, the microcomputer determines whether the clock IC has been reset by checking data held in the SRAM. The microcomputer determines failure of a water temperature sensor from a soak time calculated from time data from the clock IC and a detection value of the water temperature sensor on restarting of the engine. When the clock IC has been reset, the microcomputer prohibits this failure determination of the water temperature sensor.

6. 发明授权

US07023109B2 Uninterruptible power source apparatus 失效
标题翻译：不间断电源设备
公开(公告)号：US07023109B2
公开(公告)日：2006-04-04
申请号：US10487767
申请日：2003-03-04
申请人： Isao Amano
发明人： Isao Amano
IPC分类号： H02J7/00 , H02M7/44
CPC分类号： H02J9/062 , Y10T307/505 , Y10T307/615 , Y10T307/735
摘要： An uninterruptible power supply unit essentially includes: a DC power supply source 3, a parallel converter 4, and a series converter 6 that are individually connected in parallel to both ends of an electrolytic capacitor Cdc having a pair of capacitors C1 and C2. An input terminal Pin1 is connected to an intermediate point of the electrolytic capacitor Cdc. A power supply line 1n interlinking an input terminal Pin1 and an output terminal Pout2 is connected to multiple switching elements of the parallel converter 4 via a reactor Lin. Likewise, multiple switching elements of the series converter 6 are individually connected to an output terminal Pout1 via another reactor Lout. Multiple capacitors C individually constituting the above-described reactors L and filters are connected in parallel between the input terminals and output terminals. When any abnormality is generated in the AC input voltage, a controlling device activates operation of the parallel converter 4 so that input current Ipara flowing through the parallel converter 4 can become output current Iout, thereby generating a state equal to the case in which the input side of the AC power supply source has been disconnected from the power supply switch. Concurrently, the controlling device activates operation of the series converter 6 so that the output voltage Vout can become the series-voltage commanding value Vout*.
摘要翻译：不间断电源单元基本上包括：具有并联连接到具有一对电容器C 1和C 2的电解电容器Cdc的两端的直流电源3，并联转换器4和串联转换器6。输入端子引脚1连接到电解电容器Cdc的中间点。将输入端子Pin1和输出端子Pout2互连的电源线1 n经由电抗器Lin连接到并行变换器4的多个开关元件。同样地，串联转换器6的多个开关元件经由另一个反向器Lout单独地连接到输出端子Pout 1。单独构成上述电抗器L和滤波器的多个电容器C并联连接在输入端子和输出端子之间。当在交流输入电压中产生任何异常时，控制装置启动并行转换器4的操作，使流过并行转换器4的输入电流Ipara成为输出电流Iout，从而产生等于输入交流电源的一侧已经从电源开关断开。同时，控制装置激活串联变换器6的动作，使输出电压Vout成为串联电压指令值Vout *。

7. 发明授权

US06867106B2 Semiconductor device and method for fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06867106B2
公开(公告)日：2005-03-15
申请号：US10330113
申请日：2002-12-30
申请人： Seiichiro Yamaguchi , Mitsuaki Kai , Isao Amano
发明人： Seiichiro Yamaguchi , Mitsuaki Kai , Isao Amano
IPC分类号： H01L21/3205 , H01L23/52 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/78 , H01L29/786 , H01L21/8228
CPC分类号： H01L29/78615 , H01L29/41733 , H01L29/42384 , H01L29/458 , H01L29/78621 , H01L29/78645 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device comprises: a conducting layer including: a channel region; a source region and a drain region sandwiching the channel region; and a body region connected to the channel region and being adjacent to the source region and the drain region; a gate electrode formed above the channel region interposing a gate insulation film therebetween; a dummy electrode formed on the body region near the interface between at least the drain region and the body region, and electrically insulated with the gate electrode; and a body contact region formed in the body region except a region where the dummy electrode is formed. The gate electrode and the dummy electrode are electrically insulated with each other, whereby the semiconductor device having body contacts can have a gate capacitance much decreased. Accordingly, deterioration of the speed performance of the transistors can be suppressed.
摘要翻译：半导体器件包括：导电层，包括：沟道区; 源极区域和漏极区域，夹着沟道区域; 以及与所述沟道区域连接且与所述源极区域和所述漏极区域相邻的主体区域; 形成在所述沟道区域之上的栅极电极，所述沟道区域之间插入栅极绝缘膜; 形成在至少所述漏极区域和所述体区域之间的界面附近的所述主体区域上并与所述栅电极电绝缘的虚拟电极; 以及形成在除了形成所述虚拟电极的区域之外的所述体区域中的体接触区域。栅电极和虚拟电极彼此电绝缘，由此具有主体接触的半导体器件可以使栅电容大大降低。因此，可以抑制晶体管的速度性能的劣化。

8. 发明授权

US4287101A Enzyme-containing detergent composition 失效
标题翻译：含酶洗涤剂组合物
公开(公告)号：US4287101A
公开(公告)日：1981-09-01
申请号：US134453
申请日：1980-03-27
申请人： Hiroshi Nishio , Kazuaki Fukano , Isao Amano , Osamu Okumura
发明人： Hiroshi Nishio , Kazuaki Fukano , Isao Amano , Osamu Okumura
IPC分类号： C11D3/386 , C11D3/065
CPC分类号： C11D3/38609
摘要： An enzyme-containing detergent composition having good deterbency against, especially, soiled spots in fabrics or clothes derived from a combination of sebum from human skin, a slight amount of sweat and invisible fine dust in the air is described. This detergent composition contains (I) (a) at least one olefin sulfonate having 10 to 20 carbon atoms, (b) at least one anionic surface active agent having an SO.sub.3 or SO.sub.4 group, except for said olefin sulfonate, and (c) at least one pyrophosphate and (II) at least one enzyme, the total amount of said components (a), (b) and (c) being at least 25% by weight based on the total amount of the detergent composition and the weight ratio of (a):(b):(c) being within the area enclosed by the points A, B, C and D defined in the attached triangular diagram.
摘要翻译：描述了对来自人皮肤的皮脂组合的织物或衣服中的污染斑点，特别是空气中的少量汗液和不可见的微细粉尘具有良好的抗褪色性的含酶洗涤剂组合物。该洗涤剂组合物含有（I）（a）至少一种具有10至20个碳原子的烯烃磺酸盐，（b）至少一种具有SO 3或SO 4基团的阴离子表面活性剂，除了所述烯烃磺酸盐，和（c）至少一种焦磷酸盐和（II）至少一种酶，所述组分（a），（b）和（c）的总量相对于洗涤剂组合物的总量和重量比为至少25重量％（a）:( b）:( c）在所附的三角形图中定义的点A，B，C和D所包围的区域内。

9. 发明授权

US08183839B2 Switching power source system 有权
标题翻译：开关电源系统
公开(公告)号：US08183839B2
公开(公告)日：2012-05-22
申请号：US12457344
申请日：2009-06-08
申请人： Hideo Shimizu , Isao Amano
发明人： Hideo Shimizu , Isao Amano
IPC分类号： G05F1/70 , G05F1/613
CPC分类号： H02M1/4225 , H02M1/44 , Y02B70/126
摘要： An error voltage Verr, being a difference between DC output voltage Vout and output reference voltage Vref, and an input voltage Vin are multiplied to produce first threshold voltage signal Vth1 in phase with and similar to input voltage Vin and proportional to Verr. Second threshold voltage signal Vth2 is produced from first threshold voltage signal Vth1. The input current is detected as a current detection signal Vi across a resistor 12, whether it is between the threshold value signals is detected by a current range detecting circuit, and accordingly, the timing of turning on or off switching device is controlled so that at least one of an duration on and an off duration of the switching device is limited to enhance a power factor. Unfixed off duration disperses a noise spectrum to prevent an increase in switching frequency, to reduce noise.
摘要翻译：将作为直流输出电压Vout和输出基准电压Vref之间的差异的误差电压Verr和输入电压Vin相乘，以与输入电压Vin相同且类似于Verr成比例地产生第一阈值电压信号Vth1。从第一阈值电压信号Vth1产生第二阈值电压信号Vth2。输入电流被检测为跨过电阻器12的电流检测信号Vi，无论其是否在电流范围检测电路之间检测到阈值信号之间，因此控制开启或关闭开关装置的定时，使得在切换装置的持续时间和持续时间中的至少一个被限制以提高功率因数。未固定的关闭持续时间分散噪声频谱以防止开关频率的增加，以减少噪声。

10. 发明申请

US20090303765A1 Switching power source system 有权
标题翻译：开关电源系统
公开(公告)号：US20090303765A1
公开(公告)日：2009-12-10
申请号：US12457344
申请日：2009-06-08
申请人： Hideo Shimizu , Isao Amano
发明人： Hideo Shimizu , Isao Amano
IPC分类号： H02M7/04
CPC分类号： H02M1/4225 , H02M1/44 , Y02B70/126
摘要： An error voltage Verr, being a difference between DC output voltage Vout and output reference voltage Vref, and an input voltage Vin are multiplied to produce first threshold voltage signal Vth1 in phase with and similar to input voltage Vin and proportional to Verr. Second threshold voltage signal Vth2 is produced from first threshold voltage signal Vth1. The input current is detected as a current detection signal Vi across a resistor 12, whether it is between the threshold value signals is detected by a current range detecting circuit, and accordingly, the timing of turning on or off switching device is controlled so that at least one of an duration on and an off duration of the switching device is limited to enhance a power factor. Unfixed off duration disperses a noise spectrum to prevent an increase in switching frequency, to reduce noise.
摘要翻译：将作为直流输出电压Vout和输出基准电压Vref之间的差的误差电压Verr和输入电压Vin相乘，以与输入电压Vin相同且相似于Verr成比例地产生第一阈值电压信号Vth1。从第一阈值电压信号Vth1产生第二阈值电压信号Vth2。输入电流被检测为跨过电阻器12的电流检测信号Vi，无论其是否在电流范围检测电路之间检测到阈值信号之间，因此控制开启或关闭开关装置的定时，使得在切换装置的持续时间和持续时间中的至少一个被限制以提高功率因数。未固定的关闭持续时间分散噪声频谱以防止开关频率的增加，以减少噪声。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式