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    • 1. 发明授权
    • Lamp device
    • 灯装置
    • US08476814B2
    • 2013-07-02
    • US13130121
    • 2008-12-03
    • Takashi IbiSumio UeharaKyouichi MasekiYosuke KanoToshitaka Higuchi
    • Takashi IbiSumio UeharaKyouichi MasekiYosuke KanoToshitaka Higuchi
    • H01J5/16
    • H01J61/86G03B21/2026G03B21/2066H01J61/025
    • A light utilization efficiency of a high-pressure discharge lamp is improved even in a case of reducing the size of a reflection mirror without using an auxiliary reflection mirror. In a lamp device where a portion of lights emitted from a discharge bulb to the periphery thereof in forward and backward directions for a predetermined range of angle is reflected at a concave reflection mirror and illuminated to a light collection area of a predetermined size formed forward of the lamp, a prism surface having an angle of refracting or deflecting at least a portion of lights emitted from the discharge bulb that is not reflected at the concave reflection mirror to the light collection area is formed to the outer peripheral surface of the discharge bulb.
    • 即使在不使用辅助反射镜的情况下减小反射镜的尺寸的情况下,也能够提高高压放电灯的光利用效率。 在灯具装置中,其中从放电灯泡到其周边的光的一部分在前后方向上预定角度范围被反射到凹面反射镜并照射到形成在预定尺寸之前的预定尺寸的光收集区域 所述灯,具有使从所述放电灯发出的至少一部分的光从所述凹面反射镜向所述光收集区域反射的角度折射或偏转的棱镜表面形成在所述放电灯泡的外周面。
    • 3. 发明授权
    • Partially storing control circuit used in a memory unit
    • 在存储单元中使用的部分存储控制电路
    • US5206942A
    • 1993-04-27
    • US490447
    • 1990-03-08
    • Takashi Ibi
    • Takashi Ibi
    • G06F12/04G06F12/06
    • G06F12/04
    • Partial-store access in which a portion of data is changed, is performed using a plurality of memory banks in a memory unit. The partial store-access is performed through an interleave method in which read-data which is one word in length is read from the memory banks during an access time. The one word write-data including a portion of data which is to be changed, is registered in store-data registers. The portion of data is changed in an overwriting operation within the access time. When more than one portion of data is to be changed, such portion is also changed within the access time, but within a different register (i.e., at a later time) than the portion of the storing data initially changed. A positional signal indicating the position of the storing data which is to be changed, is stored in position-signal registers. The portions of the storing data which have been changed are combined using the positional signals, with the one word read-data read from the memory banks, thus producing rewrite-data after the access time. The rewrite-data is then restored in the memory banks.
    • 4. 发明授权
    • Error correcting and detecting system
    • 错误校正和检测系统
    • US4631725A
    • 1986-12-23
    • US686815
    • 1984-12-27
    • Moriyuki TakamuraShigeru MukasaTakashi Ibi
    • Moriyuki TakamuraShigeru MukasaTakashi Ibi
    • G06F11/10H03M13/00H03M13/19
    • G06F11/1028H03M13/19
    • An error correcting and detecting system using a parity check H-matrix divided into a plurality of block vectors each including four or three column vectors each having eight elements. In the H-matrix, (i) there are no all "0" vectors; (ii) all column vectors are different from each other; (iii) 8 column vectors each having only one "1" is included therein, (iv) each column vector has an odd number of "1's"; (v) the modulo-2 sum of any three column vectors within any block never equals any column vectors of the H-matrix; (vi) the modulo-2 sum of four column vectors within any block never equals an all "0" vector; and (vii) the modulo-2 sum of eight column vectors within any two blocks never equals an all "0" vector.
    • 使用奇偶校验H矩阵的纠错和检测系统,该奇偶校验H矩阵被分成多个块向量,每个块向量包括每个具有八个元素的四个或三个列向量。 在H矩阵中,(i)没有全部“0”向量; (ii)所有列向量彼此不同; (iii)其中包括每个仅具有一个“1”的8个列向量,(iv)每个列向量具有奇数个“1”; (v)任何块中任何三列向量的模-2之和不等于H矩阵的任何列向量; (vi)任何块内的四列向量的模-2之和不等于全“0”向量; 和(vii)任何两个块中的八个列向量的模-2之和从不等于全“0”向量。
    • 5. 发明授权
    • Memory control device and method operated in consecutive access mode
    • 内存控制装置和方法在连续访问模式下运行
    • US5619679A
    • 1997-04-08
    • US396110
    • 1995-02-28
    • Takashi Ibi
    • Takashi Ibi
    • G06F12/00G06F12/02G06F12/08
    • G06F12/0215G06F12/0897
    • A memory control device and method receives a request to transfer a series of first-unit K byte (for example, 512) data in an address space, divides the first-unit K into second-unit L (for example, 64), assigns priority levels to the second-unit L, issues plural times a data transfer instruction to transfer the L-byte data to a memory device comprising a plurality of memories operable in a consecutive access mode, and thus accesses memories in response to the request to transfer the K-byte data. The L-byte data are sequentially allocated in third units S (for example, 64) specified by the data transfer instruction to the memories. The third unit is equal to L or is obtained by dividing L, and is a multiple of an activation unit of the memories. The S-byte data are accessed in the allocated memories in the consecutive access mode.
    • 存储器控制装置和方法接收在地址空间中传送一系列第一单元K字节(例如512)数据的请求,将第一单元K划分为第二单元L(例如,64),分配 对第二单元L的优先级进行多次发送用于将L字节数据传送到包括以可连续访问模式操作的多个存储器的存储器件的数据传送指令,并且因此响应于传送请求而访问存储器 K字节数据。 L字节数据按照由数据传送指令指定的第三单元S(例如64)顺次分配给存储器。 第三单元等于L或通过分割L获得,并且是存储器的激活单元的倍数。 在连续访问模式下,在所分配的存储器中访问S字节数据。