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1. 发明授权

US06809422B2 One-chip image processing apparatus 失效
标题翻译：单片图像处理装置
公开(公告)号：US06809422B2
公开(公告)日：2004-10-26
申请号：US10622700
申请日：2003-07-21
申请人： Takahiro Saito , Kenichi Mori , Atsushi Kunimatsu
发明人： Takahiro Saito , Kenichi Mori , Atsushi Kunimatsu
IPC分类号： H01L2348
CPC分类号： G06T1/0007
摘要： A block expanding section and a plurality of pixel processing sections are formed in the same semiconductor chip. The block expanding section handles an area to be drawn in units of blocks each composed of an appropriate number of pixels and performs expansion calculation of information of a representative value of each block. Each of the plurality of pixel processing sections has a pixel expanding section and a computing section. The pixel expanding section expands information in units of pixels at least in a rectangular area from block representative point information calculated in the block expanding section. The computing section performs computation in units of pixels information-expanded by the pixel expanding section. Each of the plurality of pixel processing sections selectively performs either graphics processing performed in cooperation with the block expanding section, or image processing performed independent of the block expanding section.
摘要翻译：在相同的半导体芯片中形成块扩展部分和多个像素处理部分。块扩展部分处理以每个由适当数量的像素组成的块为单位绘制的区域，并执行每个块的代表值的信息的扩展计算。多个像素处理部中的每一个具有像素扩展部和运算部。像素扩展部分至少在矩形区域中以从块扩展部分中计算出的块代表点信息的像素为单位扩展信息。计算部以像素扩展部扩展的像素为单位进行计算。多个像素处理部分中的每一个选择性地执行与块扩展部分协同执行的图形处理，或独立于块扩展部分执行的图像处理。

2. 发明授权

US06940519B2 Graphics processor, graphics card and graphics processing system 失效
标题翻译：图形处理器，显卡和图形处理系统
公开(公告)号：US06940519B2
公开(公告)日：2005-09-06
申请号：US10619435
申请日：2003-07-16
申请人： Takahiro Saito , Atsushi Kunimatsu
发明人： Takahiro Saito , Atsushi Kunimatsu
IPC分类号： G06T15/00 , G09G5/00 , G09G5/36 , G09G5/377 , G06F12/06
CPC分类号： G06T15/80 , G06T2200/28
摘要： A graphics processor includes a shading processing section which subjects pixel data to a shading process, a first path which permits map data and texture data output from a video memory to be input to the shading processing section, a second path which permits pixel data output from the shading processing section to be output to the video memory, and a third path which permits pixel data output from a pixel expanding section to be input to the shading processing section. Further, the third path permits pixel data output from the video memory to be input to the shading processing section instead of the pixel data output from the pixel expanding section.
摘要翻译：图形处理器包括将像素数据进行阴影处理的着色处理部分，允许从视频存储器输出的地图数据和纹理数据输入到阴影处理部分的第一路径，允许从将要输出到视频存储器的阴影处理部分和允许从像素扩展部分输出的像素数据输入到阴影处理部分的第三路径。此外，第三路径允许从视频存储器输出的像素数据被输入到阴影处理部分，而不是从像素扩展部分输出的像素数据。

3. 发明授权

US08135900B2 Integrated memory management and memory management method 有权
标题翻译：集成内存管理和内存管理方法
公开(公告)号：US08135900B2
公开(公告)日：2012-03-13
申请号：US12236880
申请日：2008-09-24
申请人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda
发明人： Atsushi Kunimatsu , Hiroto Nakai , Hiroyuki Sakamoto , Kenichi Maeda
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/7201 , G06F2212/7211
摘要： An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.
摘要翻译：根据本发明的示例的集成存储器管理装置包括获取单元，其从处理器获取读取的目的地逻辑地址，地址转换单元将读取的目的地逻辑地址转换为非易失性主存储器的读取目的地物理地址，来自非易失性主存储器的访问单元读取与读取的目的地物理地址对应的数据，并且具有等于非易失性主存储器的页面大小的块大小或整数倍的大小，以及传输单元将读取的数据传送到具有取决于非易失性主存储器的页面大小的块大小或整数倍的高速缓存大小的处理器的高速缓存存储器。

4. 发明授权

US06359624B1 Apparatus having graphic processor for high speed performance 失效
标题翻译：具有用于高速性能的图形处理器的装置
公开(公告)号：US06359624B1
公开(公告)日：2002-03-19
申请号：US09274305
申请日：1999-03-23
申请人： Atsushi Kunimatsu
发明人： Atsushi Kunimatsu
IPC分类号： G06F1516
CPC分类号： G09G5/399 , G06T15/005 , G09G5/026 , G09G5/363 , G09G2340/10 , G09G2352/00
摘要： An information processing apparatus secures a wide band width in a graphics bus and draws graphics at high speed and low cost. The apparatus employs graphics processing units connected in parallel. Each of the units is formed on a chip and has a graphics processor and a graphics memory, to provide color information and select information. The outputs of the units are selected through a tournament.
摘要翻译：信息处理装置确保图形总线中的宽带宽，并且以高速和低成本绘制图形。该装置采用并行连接的图形处理单元。每个单元形成在芯片上并具有图形处理器和图形存储器，以提供颜色信息和选择信息。通过比赛选择单位的输出。

5. 发明授权

US08880836B2 Memory management device and method 有权
标题翻译：内存管理设备和方法
公开(公告)号：US08880836B2
公开(公告)日：2014-11-04
申请号：US12970145
申请日：2010-12-16
申请人： Tsutomu Owa , Masaki Miyagawa , Atsushi Kunimatsu , Mari Takada
发明人： Tsutomu Owa , Masaki Miyagawa , Atsushi Kunimatsu , Mari Takada
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F3/0616 , G06F3/0661 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7204 , G06F2212/7211 , H03M7/6088
摘要： According to one embodiment, a device includes a determination unit, compression unit, selecting unit, write updating unit, writing unit. The determination unit determines whether to compress write data based on specific information. The specific information including at least one of the type, number of accesses, access frequency and importance level of the write data. The compression unit compresses the write data when determining to compress the write data. The selecting unit selects a write region for the write data in nonvolatile memory based on the specific information. The write updating unit updates the specific information. The writing unit writes compressed write data into the write region when determining to compress the write data. The writing unit writes uncompressed write data into the write region when not determining to compress the write data.
摘要翻译：根据一个实施例，一种设备包括确定单元，压缩单元，选择单元，写入更新单元，写入单元。确定单元基于特定信息确定是否压缩写入数据。具体信息包括写入数据的类型，数量，访问频率和重要性水平中的至少一个。当确定压缩写入数据时，压缩单元压缩写入数据。选择单元基于特定信息来选择非易失性存储器中的写入数据的写入区域。写入更新单元更新特定信息。当确定压缩写入数据时，写入单元将压缩写入数据写入写入区域。当不确定压缩写入数据时，写入单元将未压缩的写入数据写入写入区域。

6. 发明授权

US07720982B2 Computer architecture and software cells for broadband networks 有权
标题翻译：宽带网络的计算机架构和软件单元
公开(公告)号：US07720982B2
公开(公告)日：2010-05-18
申请号：US11716845
申请日：2007-03-12
申请人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
发明人： Masakazu Suzuoki , Takeshi Yamazaki , Harm Peter Hofstee , Martin E. Hopkins , Charles Ray Johns , James Allan Kahle , Shigehiro Asano , Atsushi Kunimatsu
IPC分类号： G06F15/16
CPC分类号： G06F9/4862 , G06F15/16 , H04L29/06027 , H04L63/168 , H04L67/10 , H04L67/34
摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.
摘要翻译：提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。每个软件单元在网络上唯一标识。还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

7. 发明授权

US07644234B2 Information processing apparatus with a cache memory and information processing method 有权
标题翻译：具有高速缓冲存储器和信息处理方法的信息处理装置
公开(公告)号：US07644234B2
公开(公告)日：2010-01-05
申请号：US11141700
申请日：2005-05-31
申请人： Nobuo Sasaki , Takeshi Yamazaki , Atsushi Kunimatsu , Hideki Yasukawa
发明人： Nobuo Sasaki , Takeshi Yamazaki , Atsushi Kunimatsu , Hideki Yasukawa
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0844 , G06F12/0862 , G06F12/0864 , G06F2212/6024
摘要： A secondary texture cache is used commonly by a plurality of texture units, and stores part of texture data in a main memory. A cache controlling CPU controls a refill operation from the main memory to the secondary texture cache in accordance with cache misses of the plurality of texture units, so as to suppress occurrence of thrashing in the secondary texture cache. The cache controlling CPU suppresses occurrence of the refill operation when the plurality of operating units access an identical memory address with a predetermined time difference.
摘要翻译：二次纹理缓存由多个纹理单元通常使用，并将纹理数据的一部分存储在主存储器中。高速缓存控制CPU根据多个纹理单元的高速缓存未命中来控制从主存储器到次纹理高速缓存的再填充操作，以便抑制二次纹理高速缓存中的抖动的发生。当多个操作单元以预定的时间差访问相同的存储器地址时，高速缓存控制CPU抑制再填充操作的发生。

8. 发明申请

US20080244165A1 Integrated Memory Management Device and Memory Device 有权
标题翻译：集成内存管理设备和内存设备
公开(公告)号：US20080244165A1
公开(公告)日：2008-10-02
申请号：US12056501
申请日：2008-03-27
申请人： Atsushi Kunimatsu
发明人： Atsushi Kunimatsu
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/1045 , G06F12/0246 , G06F12/10
摘要： An example of a device comprises a first MMU converting a logical address into a physical address for a cache, a controller accessing the cache based on the physical address for the cache, a first storage storing history data showing an access state to a main memory outside a processor, a second storage storing relation data showing a relationship between a logical address and a physical address in the main memory, and a second MMU converting a logical address into a physical address for the main memory based on the history and relation data and accessing the main memory based on the physical address for the main memory. The first and second MMU, controller, first storage, second storage are included in the processor.
摘要翻译：设备的示例包括将逻辑地址转换为高速缓存的物理地址的第一MMU，基于高速缓存的物理地址访问高速缓存的控制器，存储向主存储器外部存取访问状态的历史数据的第一存储器处理器，存储表示主存储器中的逻辑地址和物理地址之间的关系的关系数据的第二存储器，以及基于历史和关系数据将逻辑地址转换为主存储器的物理地址的第二MMU，以及访问主存储器基于主存储器的物理地址。第一和第二MMU，控制器，第一存储，第二存储器被包括在处理器中。

9. 发明申请

US20070233975A1 DATA PROCESSOR WITH A BUILT-IN MEMORY 审中-公开
公开(公告)号：US20070233975A1
公开(公告)日：2007-10-04
申请号：US11759330
申请日：2007-06-07
申请人： Kenichi Mori , Atsushi Kunimatsu
发明人： Kenichi Mori , Atsushi Kunimatsu
IPC分类号： G06F12/00
CPC分类号： G06F13/364 , G09G3/003 , G09G5/001 , G09G5/005 , G09G5/363 , G09G2360/18
摘要： A memory-built-in data processor comprises a controller connected to an external unit and a memory via first and second buses, and a data processor performing readout/write-in of data with respect to the memory via a third bus, the controller and the second bus, the controller performing arbitration between a first access requirement input via the first bus and a second access requirement input from the data processing unit via the third bus, the memory, the first bus, the second bus, the third bus, the controller, and the data processor being integrated in an integrated circuit.

10. 发明授权

US06938149B2 Renaming apparatus and processor 失效
标题翻译：重命名设备和处理器
公开(公告)号：US06938149B2
公开(公告)日：2005-08-30
申请号：US09962197
申请日：2001-09-26
申请人： Atsushi Kunimatsu , Yukio Watanabe
发明人： Atsushi Kunimatsu , Yukio Watanabe
IPC分类号： G06F9/30 , G06F9/34 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/30076 , G06F9/3836 , G06F9/384
摘要： A renaming apparatus configured to set a correspondence between a physical register number and a logical register number. The apparatus includes a control register configured to store the correspondence between the physical register number and the logical register number and a control register setting part configured to set the control register in accordance with the content of an instruction, when an instruction for setting the correspondence between the physical register number and the logical register number is included in the issued string of instructions.
摘要翻译：一种重命名装置，被配置为设置物理寄存器号和逻辑寄存器号之间的对应关系。该装置包括：控制寄存器，用于存储物理寄存器号和逻辑寄存器号之间的对应关系;以及控制寄存器设置部，配置为根据指令的内容设置控制寄存器，当用于设置指令的内容的指令时物理寄存器号和逻辑寄存器号包含在已发出的指令串中。

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