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1. 发明授权

US06342418B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06342418B1
公开(公告)日：2002-01-29
申请号：US09233210
申请日：1999-01-20
申请人： Takaaki Murakami , Kenji Yasumura
发明人： Takaaki Murakami , Kenji Yasumura
IPC分类号： H01L218242
CPC分类号： H01L27/105 , H01L27/10808
摘要： An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a silicon substrate. A p type impurity concentration profile. includes respective peak concentrations at a dope region for forming a p type well, a p type channel cut region, and a p type channel dope region. An impurity concentration profile of the n type source/drain region crosses the p type impurity concentration profile at a low concentration, and includes phosphorus implantation regions indicating impurity concentrations respectively higher than those of the p type channel cut region and the p type channel dope region and respective peaks in impurity concentration at the neighborhood of respective depth thereof. The impurity concentration profile of the n type source/drain region has a minimum point or inflection point at the region between the impurity concentration peaks of the phosphorus implantation regions.
摘要翻译：实现了改善pn结击穿电压并减轻电场并且不会不利地影响场效应晶体管的特性的杂质浓度分布。在硅衬底上形成n型源/漏区。 p型杂质浓度分布图。包括用于形成p型阱的掺杂区域，p型沟道切割区域和p型沟道掺杂区域中的各自的峰值浓度。 n型源极/漏极区的杂质浓度分布在低浓度下与p型杂质浓度分布相交，并且包括表示杂质浓度分别高于p型沟道切割区域和p型沟道掺杂区域的磷注入区域以及其各自深度附近的杂质浓度的各峰。 n型源/漏区的杂质浓度分布在磷注入区的杂质浓度峰之间的区域具有最小点或拐点。

2. 发明授权

US6033971A Semiconductor device having an element isolating oxide film and method of manufacturing the same 有权
标题翻译：具有元件隔离氧化物膜的半导体器件及其制造方法
公开(公告)号：US6033971A
公开(公告)日：2000-03-07
申请号：US160379
申请日：1998-09-25
申请人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
发明人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/8234
CPC分类号： H01L21/823475 , H01L21/76205 , H01L21/7621 , H01L21/76216
摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.
摘要翻译：提供了一种半导体器件，其包括具有良好的上部平坦度的元件隔离氧化物膜及其制造方法。假设tG表示栅电极层6的厚度，从栅极绝缘膜5的上表面到元件隔离氧化膜4的最厚部分的上表面的高度tU和在上表面之间限定的锐角θi 元件隔离氧化膜4和栅极绝缘膜的表面被设置在由公式{θi，tU + 5443 0 = 0.82tG}表示的范围内。因此，未蚀刻部分不保留在用于图形化稍后形成的栅极电极层的蚀刻步骤。这防止了栅电极的短路。由于元件隔离氧化物膜具有改善的平坦度，所以在图案化栅极电极的步骤中可以减少活性区域中的过蚀刻量。这防止了栅极绝缘膜和下面的衬底表面的剃刮。

3. 发明授权

US5895954A Field effect transistor with impurity concentration peak under gate electrode 失效
标题翻译：栅极电极杂质浓度峰值场效应晶体管
公开(公告)号：US5895954A
公开(公告)日：1999-04-20
申请号：US917929
申请日：1997-08-27
申请人： Kenji Yasumura , Takaaki Murakami
发明人： Kenji Yasumura , Takaaki Murakami
IPC分类号： H01L29/78 , H01L21/336 , H01L29/10 , H01L21/335
CPC分类号： H01L29/6659 , H01L29/1045 , H01L29/1083
摘要： Reverse short-channel effect is suppressed in a field effect transistor with a gate having a short length. The field effect transistor comprises a p-type silicon substrate, a gate electrode, paired lightly doped source/drain regions, and paired heavily doped source/drain regions. A boron concentration peak region is formed in the silicon substrate. A boron concentration peak region positioned at an end of the gate electrode has a length d of one fourth of a length L of the gate electrode, and extends from the end to the center of the gate electrode.
摘要翻译：在具有短长度的栅极的场效应晶体管中抑制反向短沟道效应。场效应晶体管包括p型硅衬底，栅极电极，成对的轻掺杂源极/漏极区域和成对的重掺杂源极/漏极区域。在硅衬底中形成硼浓度峰值区域。位于栅电极的端部的硼浓度峰值区域具有栅电极的长度L的四分之一的长度d，并且从端极延伸到栅电极的中心。

4. 发明授权

US5880507A Semiconductor device with improved pn junction breakdown voltage 失效
标题翻译：具有改善的pn结击穿电压的半导体器件
公开(公告)号：US5880507A
公开(公告)日：1999-03-09
申请号：US919205
申请日：1997-08-28
申请人： Takaaki Murakami , Kenji Yasumura
发明人： Takaaki Murakami , Kenji Yasumura
IPC分类号： H01L21/66 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L27/105 , H01L27/10808
摘要： An impurity concentration profile that improves pn junction breakdown voltage and mitigates the electric field, and that does not adversely affect the characteristics of a field effect transistor is realized. An n type source/drain region is formed at a silicon substrate. A p type impurity concentration profile includes respective peak concentrations at a dope region for forming a p type well, a p type channel cut region, and a p type channel dope region. An impurity concentration profile of the n type source/drain region crosses the p type impurity concentration profile at a low concentration, and includes phosphorus implantation regions indicating impurity concentrations respectively higher than those of the p type channel cut region and the p type channel dope region and respective peaks in impurity concentration at the neighborhood of respective depth thereof. The impurity concentration profile of the n type source/drain region has a minimum point or inflection point at the region between the impurity concentration peaks of the phosphorus implantation regions.
摘要翻译：实现了改善pn结击穿电压并减轻电场并且不会不利地影响场效应晶体管的特性的杂质浓度分布。在硅衬底上形成n型源/漏区。 p型杂质浓度分布包括用于形成p型阱的掺杂区域，p型沟道切割区域和p型沟道掺杂区域的各自的峰值浓度。 n型源极/漏极区的杂质浓度分布在低浓度下与p型杂质浓度分布相交，并且包括表示杂质浓度分别高于p型沟道切割区域和p型沟道掺杂区域的磷注入区域以及其各自深度附近的杂质浓度的各峰。 n型源/漏区的杂质浓度分布在磷注入区的杂质浓度峰之间的区域具有最小点或拐点。

5. 发明授权

US5831323A Semiconductor device having an element isolating oxide film and method of manufacturing the same 失效
公开(公告)号：US5831323A
公开(公告)日：1998-11-03
申请号：US601662
申请日：1996-02-14
申请人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
发明人： Kaoru Motonami , Shigeru Shiratake , Hiroshi Matsuo , Yuichi Yokoyama , Kenji Morisawa , Ritsuko Gotoda , Takaaki Murakami , Satoshi Hamamoto , Kenji Yasumura , Yasuyoshi Itoh
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L21/8234 , H01L29/00
CPC分类号： H01L21/823475 , H01L21/76205 , H01L21/7621 , H01L21/76216
摘要： There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

6. 发明授权

US6081662A Semiconductor device including trench isolation structure and a method of manufacturing thereof 失效
标题翻译：包括沟槽隔离结构的半导体器件及其制造方法
公开(公告)号：US6081662A
公开(公告)日：2000-06-27
申请号：US937187
申请日：1997-09-29
申请人： Takaaki Murakami , Kenji Yasumura , Toshiyuki Oishi , Katsuomi Shiozawa
发明人： Takaaki Murakami , Kenji Yasumura , Toshiyuki Oishi , Katsuomi Shiozawa
IPC分类号： H01L21/76 , H01L21/00 , H01L21/762 , H01L29/78 , G06F17/50
CPC分类号： H01L21/76232
摘要： In a trench isolation structure having active regions at a main surface of a silicon substrate isolated by providing a gate electrode on an insulation film formed in a trench with a gate oxide film thereunder, the insulation film has a vertical cross section configuration wherein the carrier concentration of the active region at the proximity of the upper edge corner of the trench becomes lower than the carrier concentration at the center of the active region in a state where a predetermined bias voltage is applied to the gate electrode. According to this structure, electric field concentration at the edge of the trench isolation can be relaxed and generation of an inverse narrow channel effect suppressed. Therefore, the subthreshold characteristics can be improved.
摘要翻译：在沟槽隔离结构中，在硅衬底的主表面上具有有源区，通过在其上形成有栅极氧化膜的沟槽中的绝缘膜上设置栅电极而隔离，绝缘膜具有垂直截面结构，其中载流子浓度在沟槽的上边缘拐角附近的有源区域在预定偏置电压施加到栅极电极的状态下变得低于有源区域中心处的载流子浓度。根据该结构，能够缓和沟槽隔离边缘的电场集中，抑制反向窄通道效应的产生。因此，可以提高亚阈值特性。

7. 发明授权

US5623154A Semiconductor device having triple diffusion 失效
标题翻译：具有三重扩散的半导体器件
公开(公告)号：US5623154A
公开(公告)日：1997-04-22
申请号：US477697
申请日：1995-06-07
申请人： Takaaki Murakami , Kenji Yasumura , Shigeru Shiratake
发明人： Takaaki Murakami , Kenji Yasumura , Shigeru Shiratake
IPC分类号： H01L21/76 , H01L21/336 , H01L29/06 , H01L29/78 , H01L29/76
CPC分类号： H01L29/0638 , H01L29/7833
摘要： An isolating/insulating film is formed on the surface of a p.sup.- silicon substrate in an element isolating region. An nMOS transistor having a pair of n-type source/drain regions is formed within an element forming region isolated by the isolating oxide film. A p.sup.+ impurity diffusion region is formed on the p.sup.- silicon substrate in such a manner as to be contacted with the lower surface of the isolating oxide film in the element isolating region and to extend at a specified depth from the surface of the p.sup.- silicon substrate in the element forming region. A p-type impurity diffusion region having a p-type impurity concentration higher than that of the p.sup.- silicon substrate is formed at the side end portion of the isolating oxide film in such a manner as to be contacted with the n-type source/drain region. With this arrangement, it is possible to reduce leakage current caused by the distribution of crystal defects in a depletion layer.
摘要翻译：在元件隔离区域中的p-硅衬底的表面上形成隔离/绝缘膜。在由隔离氧化膜隔离的元件形成区域内形成具有一对n型源极/漏极区域的nMOS晶体管。在p-硅衬底上形成p +杂质扩散区，以便与元件隔离区中的隔离氧化膜的下表面接触，并在p硅表面的特定深度延伸基板在元件形成区域中。在隔离氧化膜的侧端部形成p型杂质浓度高于p硅衬底的p型杂质浓度区域，以与n型源极/ 漏区。通过这种布置，可以减少由耗尽层中的晶体缺陷的分布引起的漏电流。

8. 发明申请

US20080239010A1 HEAD MODULE, LIQUID DISCHARGE HEAD, AND LIQUID DISCHARGE APPARATUS 失效
标题翻译：头部模块，液体排放头和液体排放装置
公开(公告)号：US20080239010A1
公开(公告)日：2008-10-02
申请号：US12052391
申请日：2008-03-20
申请人： Manabu Tomita , Shogo Ono , Iwao Ushinohama , Takaaki Murakami
发明人： Manabu Tomita , Shogo Ono , Iwao Ushinohama , Takaaki Murakami
IPC分类号： B41J2/05
CPC分类号： B41J2/14072 , B41J2/1603 , B41J2/1623 , B41J2/1631 , B41J2/1632 , B41J2/1645 , B41J2202/20
摘要： A head module includes lines of head chips, each head chip having energy-generating elements for discharging liquid and electrodes for electrically connecting the energy-generating elements to a control substrate, and a wiring board having wires for electrically connecting the electrodes to the control substrate. The head module drives the energy-generating elements through the wiring board to discharge liquid. The wiring board includes connecting sections connecting the wires to the respective electrodes, common wire sections joining some of the wires that are common to the head chips, and a terminal section connecting the wires to the control substrate at one side of the wiring board. The wires in the connecting and terminal sections are arranged in a single-layer structure along a horizontal direction. The wires in the common wire sections are arranged in a multi-layer structure in which portions of the wires are stacked in the vertical direction.
摘要翻译：头模块包括头芯片，每个头芯片具有用于排出液体的能量产生元件和用于将能量产生元件电连接到控制基板的电极，以及具有用于将电极电连接到控制基板的导线的布线板。头模块通过布线板驱动发电元件以排出液体。布线板包括将导线连接到各个电极的连接部分，连接头部芯片共有的一些电线的公共电线部分和将电线连接到布线板一侧的控制基板的端子部分。连接端子和端子部分中的导线沿水平方向布置成单层结构。公共电线部分中的电线布置成多层结构，其中电线的一部分在垂直方向上堆叠。

9. 发明授权

US07205761B2 Rotation state detecting device and rotation state detecting method 有权
标题翻译：旋转状态检测装置和旋转状态检测方法
公开(公告)号：US07205761B2
公开(公告)日：2007-04-17
申请号：US11076874
申请日：2005-03-11
申请人： Manabu Tsukamoto , Takaaki Murakami , Yuji Ariyoshi , Takahiro Ohnakado , Yasuhiro Kosasayama
发明人： Manabu Tsukamoto , Takaaki Murakami , Yuji Ariyoshi , Takahiro Ohnakado , Yasuhiro Kosasayama
IPC分类号： G01P3/44 , G01B7/30 , G08B21/00
CPC分类号： G01D5/145 , G01D5/2451
摘要： A rotation state detecting device capable of detecting the direction of rotation of a rotating body includes first and second bridge circuits made up of magneto-resistance effect elements, a first comparator for detecting the increasing/decreasing direction of the center point voltage of the first bridge circuit, a second comparator for detecting the increasing/decreasing direction of the center point voltage of the second bridge circuit, a third comparator for detecting the difference between the center point voltage of the first bridge circuit and the center point voltage of the second bridge circuit, and logic value information deriving means for outputting “1” when the logic values of the outputs of the first comparator and the second comparator are both “1”, outputting “0” when they are both “0”, and continuing to output the previous value at other times, the direction of rotation of the rotating body being determined on the basis of a combination of the outputs of the first, second and third comparators and the logic value information deriving means.
摘要翻译：能够检测旋转体的旋转方向的旋转状态检测装置包括由磁阻效应元件构成的第一和第二桥接电路，用于检测第一桥的中心点电压的增减方向的第一比较器电路，用于检测第二桥接电路的中心点电压的增加/减少方向的第二比较器，用于检测第一桥接电路的中心点电压与第二桥接电路的中心点电压之间的差的第三比较器以及当第一比较器和第二比较器的输出的逻辑值都为“1”时输出“1”的逻辑值信息导出装置，当它们均为“0”时输出“0”，并且继续输出在其他时刻的先前值，旋转体的旋转方向基于第一，第二的输出的组合来确定 nd和第三比较器以及逻辑值信息导出装置。

10. 发明申请

US20050248614A1 Liquid discharge apparatus, printer head, and method for making liquid discharge apparatus 审中-公开
公开(公告)号：US20050248614A1
公开(公告)日：2005-11-10
申请号：US11145092
申请日：2005-06-03
申请人： Takaaki Murakami , Minoru Kohno , Koichi Igarashi , Shogo Ono , Toru Tanikawa
发明人： Takaaki Murakami , Minoru Kohno , Koichi Igarashi , Shogo Ono , Toru Tanikawa
IPC分类号： B41J2/135 , B41J2/05 , B41J2/14 , B41J2/145 , B41J2/15 , B41J2/16 , B65D81/24
CPC分类号： B41J2/1626 , B41J2/14024 , B41J2/1603 , B41J2/1623 , B41J2/1631 , B41J2/1642 , B41J2/1643 , B41J2/1645
摘要： A liquid discharge apparatus has liquid chambers and nozzles that discharge droplets of liquids contained in the liquid chambers through liquid channels. The liquid discharge apparatus includes a substrate provided with partitions on one face thereof, the liquid chambers and the liquid channels being defined between the partitions. The liquid discharge apparatus further includes a nozzle sheet provided with adhesion-improving layers at least at positions corresponding to the top faces of the partitions and the nozzles for discharging liquid, the nozzle sheet and the top faces of the respective partitions being bonded to each other with the adhesion-improving layers. The liquid discharge apparatus also includes driving elements provided on the face of the substrate at positions corresponding to the liquid chambers, for changing the pressure of the liquid chambers. The liquid discharge apparatus is used as a printer head for ink jet printing.

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