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1. 发明授权

US09356020B2 Semiconductor arrangement 有权
标题翻译：半导体安排
公开(公告)号：US09356020B2
公开(公告)日：2016-05-31
申请号：US14289766
申请日：2014-05-29
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Sang Hoo Dhong , Ta-Pen Guo , Chung-Cheng Wu
IPC分类号： H01L29/10 , H01L21/02 , H01L27/088 , H01L29/06 , H01L29/78 , H01L29/66 , B82Y10/00 , B82Y40/00 , H01L29/423 , H01L29/775 , H01L21/8234
CPC分类号： H01L21/82385 , B82Y10/00 , B82Y40/00 , H01L21/823456 , H01L21/823487 , H01L21/823807 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L29/0676 , H01L29/42392 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827 , H01L29/78642 , H01L29/78696
摘要： A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.
摘要翻译：半导体装置包括第一半导体器件，其包括具有第一导电类型的第一类型区域和具有第二导电类型的第二类型区域。半导体装置包括与第一半导体器件相邻的第二半导体器件。第二半导体器件包括具有第三导电类型的第三类型区域和具有第四导电类型的第四类型区域。半导体装置包括第一绝缘体层，其包括围绕第一半导体器件中的至少一些的第一绝缘体部分和围绕第二半导体器件的至少一部分的第二绝缘体部分。第一绝缘体部分具有第一绝缘体高度，并且第二绝缘体部分具有第二绝缘体高度。第一绝缘体高度不同于第二绝缘体高度。提供一种形成半导体装置的方法。

2. 发明申请

US20150286760A1 SCAN CELL ASSIGNMENT 有权
标题翻译：扫描单元分配
公开(公告)号：US20150286760A1
公开(公告)日：2015-10-08
申请号：US14243975
申请日：2014-04-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Cheng-Chung Lin , Ming-Zhang Kuo , Sang Hoo Dhong , Ho-Chieh Hsieh , Kuo Feng Tseng
IPC分类号： G06F17/50 , G01R31/3177
CPC分类号： G06F17/5045 , G06F17/505 , G06F2217/14
摘要： One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.
摘要翻译：提供了一种或多种用于半导体布置的设计布局的扫描单元分配的系统和方法。评估设计布局以识别一组顺序单元，例如通过数据路径连接到电路的触发器。基于控制路径标准，寄存器组标准，流水线深度标准，顺序循环标准或其他创建标准，将顺序单元组内的顺序单元分配给扫描单元分配或非扫描单元分配单元格分配列表。扫描路径被连接到分配给扫描单元分配的顺序单元，使得测试模式可以在用于缺陷的半导体布置的测试期间发送到这样的顺序单元并从其接收。功率，性能和面积利用率得到改善，因为至少一些顺序单元被分配给非扫描单元分配。

3. 发明申请

US20150069501A1 SEMICONDUCTOR ARRANGEMENT 有权
标题翻译：半导体安排
公开(公告)号：US20150069501A1
公开(公告)日：2015-03-12
申请号：US14289766
申请日：2014-05-29
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Sang Hoo Dhong , Ta-Pen Guo , Chung-Cheng Wu
IPC分类号： H01L29/10 , H01L27/088 , H01L29/78 , H01L29/06 , H01L21/02
CPC分类号： H01L21/82385 , B82Y10/00 , B82Y40/00 , H01L21/823456 , H01L21/823487 , H01L21/823807 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L29/0676 , H01L29/42392 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827 , H01L29/78642 , H01L29/78696
摘要： A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.
摘要翻译：半导体装置包括第一半导体器件，其包括具有第一导电类型的第一类型区域和具有第二导电类型的第二类型区域。半导体装置包括与第一半导体器件相邻的第二半导体器件。第二半导体器件包括具有第三导电类型的第三类型区域和具有第四导电类型的第四类型区域。半导体装置包括第一绝缘体层，其包括围绕第一半导体器件中的至少一些的第一绝缘体部分和围绕第二半导体器件的至少一部分的第二绝缘体部分。第一绝缘体部分具有第一绝缘体高度，并且第二绝缘体部分具有第二绝缘体高度。第一绝缘体高度不同于第二绝缘体高度。提供一种形成半导体装置的方法。

4. 发明申请

US20160268168A1 SEMICONDUCTOR ARRANGEMENT 审中-公开
公开(公告)号：US20160268168A1
公开(公告)日：2016-09-15
申请号：US15160206
申请日：2016-05-20
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Chung-Cheng Wu , Sang Hoo Dhong , Ta-Pen Guo
IPC分类号： H01L21/8238 , H01L29/423 , H01L29/786 , H01L27/092 , H01L29/06
CPC分类号： H01L21/82385 , B82Y10/00 , B82Y40/00 , H01L21/823456 , H01L21/823487 , H01L21/823807 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L29/0676 , H01L29/42392 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827 , H01L29/78642 , H01L29/78696
摘要： A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.

5. 发明授权

US09620422B2 Semiconductor arrangement 有权
公开(公告)号：US09620422B2
公开(公告)日：2017-04-11
申请号：US15160206
申请日：2016-05-20
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Jean-Pierre Colinge , Chung-Cheng Wu , Sang Hoo Dhong , Ta-Pen Guo
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/786 , H01L29/78 , H01L27/088 , H01L29/66 , B82Y10/00 , B82Y40/00 , H01L29/775 , H01L21/8234
CPC分类号： H01L21/82385 , B82Y10/00 , B82Y40/00 , H01L21/823456 , H01L21/823487 , H01L21/823807 , H01L21/823885 , H01L27/088 , H01L27/092 , H01L29/0676 , H01L29/42392 , H01L29/66439 , H01L29/66666 , H01L29/775 , H01L29/7827 , H01L29/78642 , H01L29/78696
摘要： A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.

6. 发明授权

US09495495B2 Scan cell assignment 有权
标题翻译：扫描单元格分配
公开(公告)号：US09495495B2
公开(公告)日：2016-11-15
申请号：US14243975
申请日：2014-04-03
申请人： Taiwan Semiconductor Manufacturing Company Limited
发明人： Cheng-Chung Lin , Ming-Zhang Kuo , Sang Hoo Dhong , Ho-Chieh Hsieh , Kuo Feng Tseng
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5045 , G06F17/505 , G06F2217/14
摘要： One or more systems and methods for scan cell assignment for a design layout of a semiconductor arrangement are provided. The design layout is evaluated to identify a set of sequential cells, such as flip flops connected to circuitry by data paths. Sequential cells within the set of sequential cells are assigned to either a scan cell assignment or a non-scan cell assignment based upon a control path criterion, a register bank criterion, a pipeline depth criterion, a sequential loop criterion, or other criteria to create a cell assignment list. Scan paths are connected to sequential cells assigned to the scan cell assignment so that test patterns can be sent to and received from such sequential cells during testing of the semiconductor arrangement for defects. Power, performance, and area utilization are improved because at least some sequential cells are assigned to the non-scan cell assignment.
摘要翻译：提供了一种或多种用于半导体布置的设计布局的扫描单元分配的系统和方法。评估设计布局以识别一组顺序单元，例如通过数据路径连接到电路的触发器。基于控制路径标准，寄存器组标准，流水线深度标准，顺序循环标准或其他创建标准，将顺序单元组内的顺序单元分配给扫描单元分配或非扫描单元分配单元格分配列表。扫描路径被连接到分配给扫描单元分配的顺序单元，使得测试模式可以在用于缺陷的半导体布置的测试期间发送到这样的顺序单元并从其接收。功率，性能和面积利用率得到改善，因为至少一些顺序单元被分配给非扫描单元分配。

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