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1. 发明申请

US20180040617A1 Method and Structure for Gap Filling Improvement 审中-公开
公开(公告)号：US20180040617A1
公开(公告)日：2018-02-08
申请号：US15783448
申请日：2017-10-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ying-Hao Su , Yu-Chung Su , Yu-Lun Liu , Chi-Kang Chang , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L27/088 , H01L21/027 , H01L21/768 , H01L21/02 , H01L29/66 , H01L21/8234
摘要： Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

2. 发明授权

US08906595B2 Method for improving resist pattern peeling 有权
标题翻译：改善抗蚀剂图案剥离的方法
公开(公告)号：US08906595B2
公开(公告)日：2014-12-09
申请号：US13666107
申请日：2012-11-01
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Chie-Chieh Lin
IPC分类号： G03F7/26 , G03F1/00
CPC分类号： G03F1/38 , G03F1/00 , G03F7/70433
摘要： A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.
摘要翻译：描述制造掩模的方法。该方法包括接收接收具有包括第一特征的第一图案层并且具有包括第二特征的第二图案层的集成电路（IC）设计布局，其中当形成第一图案层和第二图案层时，第一图案层和第二图案层在空间上相关基板，使得第一和第二特征在第一特征的第一边缘和第二特征的第二边缘之间隔开第一距离，通过基于第一距离调整第一特征的尺寸来修改IC设计布局，以及从用于掩模制作的修改的IC设计布局生成带出数据。该方法还包括将逻辑运算（LOP）应用于IC设计布局。

3. 发明公开

US20240387430A1 METAL BUMP STRUCTURES AND METHODS OF FORMING THE SAME 审中-公开
公开(公告)号：US20240387430A1
公开(公告)日：2024-11-21
申请号：US18365667
申请日：2023-08-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chang-Jung Hsueh , Chieh-Ning Feng , Yu-Lun Liu , Wen-Hsiung Lu , Ming-Da Cheng
IPC分类号： H01L23/00
CPC分类号： H01L24/13 , H01L24/11 , H01L2224/11462 , H01L2224/11903 , H01L2224/11916 , H01L2224/13006 , H01L2224/13008 , H01L2224/13014 , H01L2224/13017 , H01L2224/13147 , H01L2924/01029 , H01L2924/35121
摘要： Semiconductor structures and methods are provided. An exemplary semiconductor structure includes a contact pad over a substrate, an under-bump metallization (UBM) layer over the contact pad, a metal pillar over first UBM layer and electrically coupled to the contact pad via the UBM layer, and a solder cap on the metal pillar. The metal pillar comprises copper, and a percentage of (111) crystal orientation of the copper is 90% or more.

4. 发明授权

US10515953B2 Method and structure for gap filling improvement 有权
公开(公告)号：US10515953B2
公开(公告)日：2019-12-24
申请号：US15783448
申请日：2017-10-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ying-Hao Su , Yu-Chung Su , Yu-Lun Liu , Chi-Kang Chang , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/02 , H01L21/027 , H01L29/66 , H01L21/768
摘要： Semiconductor devices having void-free dielectric structures and methods of fabricating same are disclosed herein. An exemplary semiconductor device includes a plurality of fin structures disposed over a substrate having isolation features disposed therein and a plurality of gate structures disposed over the plurality of fin structures. The plurality of gate structures traverse the plurality of fin structures. The semiconductor device further includes a dielectric structure defined between the plurality of fin structures and the plurality of gate structures. The dielectric structure has an aspect ratio of about 5 to about 16. The dielectric structure includes a first dielectric layer disposed over the substrate and a second dielectric layer disposed on the first dielectric layer. The first dielectric layer and the second dielectric layer are disposed on sidewalls of the plurality of fin structures and sidewalls of the plurality of gate structures.

5. 发明授权

US09793268B2 Method and structure for gap filling improvement 有权
公开(公告)号：US09793268B2
公开(公告)日：2017-10-17
申请号：US14163843
申请日：2014-01-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ying-Hao Su , Yu-Chung Su , Yu-Lun Liu , Chi-Kang Chang , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/02 , H01L21/027 , H01L29/66 , H01L21/768
CPC分类号： H01L27/0886 , H01L21/02118 , H01L21/02282 , H01L21/02299 , H01L21/02318 , H01L21/0276 , H01L21/76837 , H01L21/823431 , H01L21/823437 , H01L29/66795
摘要： The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.

6. 发明授权

US09274414B2 Method for making a lithography mask 有权
标题翻译：光刻掩模的制造方法
公开(公告)号：US09274414B2
公开(公告)日：2016-03-01
申请号：US14558842
申请日：2014-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Chie-Chieh Lin
IPC分类号： G03F1/38 , G03F1/00
CPC分类号： G03F1/38 , G03F1/00 , G03F7/70433
摘要： A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.
摘要翻译：描述制造掩模的方法。该方法包括接收接收具有包括第一特征的第一图案层并且具有包括第二特征的第二图案层的集成电路（IC）设计布局，其中当形成第一图案层和第二图案层时，第一图案层和第二图案层在空间上相关基板，使得第一和第二特征在第一特征的第一边缘和第二特征的第二边缘之间隔开第一距离，通过基于第一距离调整第一特征的尺寸来修改IC设计布局，以及从用于掩模制作的修改的IC设计布局生成带出数据。该方法还包括将逻辑运算（LOP）应用于IC设计布局。

7. 发明申请

US20150214226A1 METHOD AND STRUCTURE FOR GAP FILLING IMPROVEMENT 有权
标题翻译： GAP填充改进方法与结构
公开(公告)号：US20150214226A1
公开(公告)日：2015-07-30
申请号：US14163843
申请日：2014-01-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ying-Hao SU , Yu-Chung Su , Yu-Lun Liu , Chi-Kang Chang , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L27/088 , H01L21/033 , H01L21/027 , H01L21/8234 , H01L21/02
CPC分类号： H01L27/0886 , H01L21/02118 , H01L21/02282 , H01L21/02299 , H01L21/02318 , H01L21/0276 , H01L21/76837 , H01L21/823431 , H01L21/823437 , H01L29/66795
摘要： The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.
摘要翻译：本公开提供了一种用于形成半导体结构的方法。该方法包括在衬底上提供包括多个翅片结构的衬底; 在所述基板上涂覆第一溶液以形成第一介电层; 以及在所述第一介电层上涂覆第二溶液以形成覆盖所述翅片结构的第二介电层。第一溶液具有第一粘度。第二溶液具有第二粘度。在一些实施方案中，第二粘度大于第一粘度。

8. 发明申请

US20150086910A1 METHOD FOR MAKING A LITHOGRAPHY MASK 有权
标题翻译：制作光刻面膜的方法
公开(公告)号：US20150086910A1
公开(公告)日：2015-03-26
申请号：US14558842
申请日：2014-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Chie-Chieh Lin
IPC分类号： G03F1/38
CPC分类号： G03F1/38 , G03F1/00 , G03F7/70433
摘要： A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.
摘要翻译：描述制造掩模的方法。该方法包括接收接收具有包括第一特征的第一图案层并且具有包括第二特征的第二图案层的集成电路（IC）设计布局，其中当形成第一图案层和第二图案层时，第一图案层和第二图案层在空间上相关基板，使得第一和第二特征在第一特征的第一边缘和第二特征的第二边缘之间隔开第一距离，通过基于第一距离调整第一特征的尺寸来修改IC设计布局，以及从用于掩模制作的修改的IC设计布局生成带出数据。该方法还包括将逻辑运算（LOP）应用于IC设计布局。

9. 发明申请

US20140120729A1 METHOD FOR REMOVING A PATTERNED HARD MASK LAYER 审中-公开
标题翻译：用于去除图案硬掩模层的方法
公开(公告)号：US20140120729A1
公开(公告)日：2014-05-01
申请号：US13666268
申请日：2012-11-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yu-Lun Liu , Ying-Hao Su , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L21/308 , G06F17/50
CPC分类号： G06F17/50 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32139
摘要： The present disclosure provides embodiments of a method that includes providing a substrate having a patterned material layer and a patterned hard mask layer disposed on the patterned material layer, wherein the patterned material layer includes a material feature having a first dimension and the patterned hard mask layer includes a hard mask feature covering the material feature. The method also includes forming, on the substrate and the hard mask feature, a patterned resist layer with an opening that exposes the hard mask feature and has a second dimension as a function of the first dimension; etching back the resist film; and removing the patterned hard mask layer.
摘要翻译：本公开提供了一种方法的实施例，其包括提供具有图案化材料层和设置在图案化材料层上的图案化硬掩模层的衬底，其中图案化材料层包括具有第一尺寸的材料特征和图案化硬掩模层包括覆盖材料特征的硬掩模特征。该方法还包括在衬底和硬掩模特征上形成具有暴露硬掩模特征并具有作为第一尺寸的函数的第二尺寸的开口的图案化抗蚀剂层; 蚀刻抗蚀剂膜; 并去除图案化的硬掩模层。

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