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1. 发明申请

US20220328482A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME 有权
公开(公告)号：US20220328482A1
公开(公告)日：2022-10-13
申请号：US17225907
申请日：2021-04-08
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Wen-Ting Lan , Shi Ning Ju , Kuo-Cheng Chiang , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L27/092 , H01L29/417 , H01L29/78 , H01L29/66 , H01L21/8234
摘要： A semiconductor device structure, along with methods of forming such, are described. The structure includes a semiconductor fin having a first portion having a first width and a second portion having a second width substantially less than the first width. The first portion has a first surface, the second portion has a second surface, and the first and second surfaces are connected by a third surface. The third surface forms an angle with respect to the second surface, and the angle ranges from about 90 degrees to about 130 degrees. The structure further includes a gate electrode layer disposed over the semiconductor fin and source/drain epitaxial features disposed on the semiconductor fin on opposite sides of the gate electrode layer.

2. 发明授权

US11462612B2 Semiconductor device structure 有权
公开(公告)号：US11462612B2
公开(公告)日：2022-10-04
申请号：US17142970
申请日：2021-01-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Jung-Chien Cheng , Shi Ning Ju , Guan-Lin Chen , Kuo-Cheng Chiang , Chih-Hao Wang , Kuan-Lun Cheng
IPC分类号： H01L29/00 , H01L27/082 , H01L27/102 , H01L29/06 , H01L29/78 , H01L21/8234 , H01L29/66
摘要： Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a substrate having a p-type well or an n-type well, a first base portion over the p-type well, a second base portion over the n-type well, a first plurality of channel members over the first base portion, a second plurality of channel members over the second base portion, an isolation feature disposed between the first base portion and the second base portion, and a deep isolation structure in the substrate disposed below the isolation feature.

3. 发明申请

US20220216346A1 CAPACITANCE REDUCTION FOR BACK-SIDE POWER RAIL DEVICE 有权
公开(公告)号：US20220216346A1
公开(公告)日：2022-07-07
申请号：US17703116
申请日：2022-03-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shi Ning Ju , Chih-Hao Wang , Kuo-Cheng Chiang , Kuan-Lun Cheng , Wen-Ting Lan
IPC分类号： H01L29/786 , H01L29/417 , H01L29/423 , H01L29/66
摘要： A semiconductor transistor device includes a channel structure, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, a gate contact, and a back-side source/drain contact. The gate structure wraps around the channel structure. The first source/drain epitaxial structure and the second source/drain epitaxial structure are disposed on opposite endings of the channel structure. The gate contact is disposed on the gate structure. The back-side source/drain contact is disposed under the first source/drain epitaxial structure. The first source/drain epitaxial structure has a concave bottom surface contacting the back-side source/drain contact.

4. 发明授权

US11114529B2 Gate-all-around field-effect transistor device 有权
公开(公告)号：US11114529B2
公开(公告)日：2021-09-07
申请号：US16550049
申请日：2019-08-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Chiang , Huan-Chieh Su , Shi Ning Ju , Kuan-Ting Pan , Chih-Hao Wang
IPC分类号： H01L29/06 , H01L21/02 , H01L21/308 , H01L21/8234 , H01L29/66 , H01L21/311 , H01L21/3065 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/08 , H01L21/762 , H01L29/10
摘要： A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

5. 发明申请

US20210057525A1 GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICE 有权
公开(公告)号：US20210057525A1
公开(公告)日：2021-02-25
申请号：US16550049
申请日：2019-08-23
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Chiang , Huan-Chieh Su , Shi Ning Ju , Kuan-Ting Pan , Chih-Hao Wang
IPC分类号： H01L29/06 , H01L21/8234 , H01L21/308 , H01L21/02 , H01L29/66 , H01L21/311 , H01L21/3065 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/08 , H01L21/762 , H01L29/10
摘要： A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

6. 发明申请

US20190140075A1 FinFET With a Semiconductor Strip as a Base 审中-公开
公开(公告)号：US20190140075A1
公开(公告)日：2019-05-09
申请号：US16222131
申请日：2018-12-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Ching , Shi Ning Ju , Ching-Wei Tsai , Chih-Hao Wang , Ying-Keung Leung , Carlos H Diaz
IPC分类号： H01L29/66 , H01L29/78 , H01L29/08 , H01L29/165
CPC分类号： H01L29/66545 , H01L29/0847 , H01L29/165 , H01L29/66795 , H01L29/785
摘要： A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

7. 发明授权

US10269803B2 Hybrid scheme for improved performance for P-type and N-type FinFETs 有权
公开(公告)号：US10269803B2
公开(公告)日：2019-04-23
申请号：US15691852
申请日：2017-08-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Ching , Shi Ning Ju , Ching-Wei Tsai , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L21/02 , H01L29/04 , H01L29/06 , H01L29/66 , H01L29/78 , H01L21/306 , H01L21/311 , H01L21/762 , H01L27/092 , H01L21/8238 , H01L29/165
摘要： A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.

8. 发明申请

US20180097114A1 FinFET With a Semiconductor Strip as a Base 审中-公开
公开(公告)号：US20180097114A1
公开(公告)日：2018-04-05
申请号：US15819952
申请日：2017-11-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Ching , Shi Ning Ju , Ching-Wei Tsai , Chih-Hao Wang , Ying-Keung Leung , Carlos H. Diaz
IPC分类号： H01L29/78 , H01L29/24 , H01L29/06 , H01L29/08 , H01L29/161 , H01L29/165 , H01L29/267 , H01L29/66
CPC分类号： H01L29/66545 , H01L29/0653 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.

9. 发明申请

US20140141582A1 CMOS DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译： CMOS器件及其形成方法
公开(公告)号：US20140141582A1
公开(公告)日：2014-05-22
申请号：US14170102
申请日：2014-01-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kuo-Cheng Ching , Shi Ning Ju , Cary Chia-Chiung Lo , Huicheng Chang , Chun Chung Su
IPC分类号： H01L21/8238
CPC分类号： H01L21/823821 , H01L21/823807 , H01L21/823878 , H01L27/0922 , H01L27/0924
摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a first region and a second region. The semiconductor device further includes a first buffer layer formed over the substrate and between first and second isolation regions in the first region and a second buffer layer formed over the substrate and between first and second isolation regions in the second region. The semiconductor device further includes a first fin structure formed over the first buffer layer and between the first and second isolation regions in the first region and a second fin structure formed over the second buffer layer and between the first and second isolation regions in the second region. The first buffer layer includes a top surface different from a top surface of the second buffer layer.
摘要翻译：公开了一种用于制造半导体器件的半导体器件和方法。示例性的半导体器件包括包括第一区域和第二区域的衬底。半导体器件还包括形成在衬底上并且在第一区域中的第一和第二隔离区域之间的第一缓冲层，以及形成在衬底上以及第二区域中的第一和第二隔离区域之间的第二缓冲层。半导体器件还包括形成在第一缓冲层之上且在第一区域中的第一和第二隔离区之间的第一鳍结构，以及形成在第二缓冲层之上以及在第二区中的第一和第二隔离区之间的第二鳍结构。第一缓冲层包括与第二缓冲层的顶表面不同的顶表面。

10. 发明授权

US08633516B1 Source/drain stack stressor for semiconductor device 有权
标题翻译：半导体器件的源极/漏极堆叠应力源
公开(公告)号：US08633516B1
公开(公告)日：2014-01-21
申请号：US13631688
申请日：2012-09-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Zhiqiang Wu , Gwan Sin Chang , Kuo-Cheng Ching , Chun Chung Su , Shi Ning Ju
IPC分类号： H01L29/66
CPC分类号： H01L29/1054 , H01L29/66795 , H01L29/785
摘要： The present disclosure provides a semiconductor device. The device includes a substrate, a fin structure formed by a first semiconductor material, a gate region on a portion of the fin, a source region and a drain region separated by the gate region on the substrate and a source/drain stack on the source and drain region. A low portion of the source/drain stack is formed by a second semiconductor material and it contacts a low portion of the fin in the gate region. An upper portion of the source/drain stack is formed by a third semiconductor material and it contacts an upper portion of the fin in the gate region.
摘要翻译：本发明提供一种半导体器件。该器件包括衬底，由第一半导体材料形成的鳍结构，鳍的一部分上的栅极区，由衬底上的栅极区分离的源极区和漏极区以及源极上的源极/漏极叠层和漏极区。源极/漏极堆叠的低部分由第二半导体材料形成，并且其在栅极区域中接触鳍片的低部分。源极/漏极堆叠的上部由第三半导体材料形成，并且在栅极区域中接触鳍片的上部。

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