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1. 发明授权

US09099540B2 Three-dimensional system-in-package architecture 有权
标题翻译：三维系统级封装架构
公开(公告)号：US09099540B2
公开(公告)日：2015-08-04
申请号：US13864112
申请日：2013-04-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oscar M. K. Law , Kuo H. Wu
IPC分类号： H01L21/44 , H01L21/768 , H01L23/48 , H01L23/00 , H01L25/065 , H01L25/00
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/13099 , H01L2224/05552
摘要： A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.
摘要翻译：公开了一种用于通过硅通孔（TSV）制造半导体管芯连接的系统和方法。制造半导体管芯，其具有通孔第一TSV以及通孔最终TSV，以便建立用于相邻管芯之间的管芯连接的低电阻路径，以及为多个管芯之间的穿通通道提供低电阻路径。

2. 发明授权

US08589847B2 Circuits and methods for programmable transistor array 有权
标题翻译：可编程晶体管阵列的电路和方法
公开(公告)号：US08589847B2
公开(公告)日：2013-11-19
申请号：US13674800
申请日：2012-11-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oscar M. K. Law , Kuo H. Wu
IPC分类号： G06F17/50
CPC分类号： H03K19/17728 , G06F17/5054 , H03K19/17796
摘要： A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit.
摘要翻译：公开了一种可编程晶体管阵列电路，其包括半导体衬底; 以及以均匀间隔的单元的行和列排列的多个基本晶体管单元（BTU），所述BTU还包括PMOS晶体管单元（PTU），NMOS晶体管单元（NTU）和虚拟晶体管单元（DTU），每个BTU具有布置在其中的导体通过BTU延伸的单个方向和导体相对于彼此均匀间隔开。 BTU的安排受限于设计规则。逻辑晶体管单元（LTU）由使用第一和第二层金属化的BTU形成。公开了结合可编程晶体管阵列电路的另外的实施例。

3. 发明申请

US20130316530A1 Three-Dimensional Semiconductor Architecture 有权
标题翻译：三维半导体架构
公开(公告)号：US20130316530A1
公开(公告)日：2013-11-28
申请号：US13957701
申请日：2013-08-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oscar M.K. Law , Kuo H. Wu
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L21/768 , H01L21/76877 , H01L21/8221 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/5286 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/83 , H01L25/0657 , H01L27/0688 , H01L27/1203 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/05552
摘要： A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. TSVs are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment this allows these connections to be made throughout the substrate instead of on the periphery of the substrate. In another embodiment, the TSVs are used as part of a power matrix to supply power and ground connections to the active devices and metallization layers through the substrate.
摘要翻译：公开了一种用于通过硅通孔（TSV）制造半导体管芯连接的系统和方法。 TSV通过衬底形成，以允许信号连接以及电源和接地连接。在一个实施例中，这允许在整个基板上进行这些连接，而不是在基板的外围。在另一个实施例中，TSV被用作功率矩阵的一部分，以通过衬底向有源器件和金属化层提供电源和接地连接。

4. 发明申请

US20130230985A1 Three-Dimensional System-in-Package Architecture 审中-公开
标题翻译：三维系统级封装体系结构
公开(公告)号：US20130230985A1
公开(公告)日：2013-09-05
申请号：US13864112
申请日：2013-04-16
申请人： Taiwan Semiconductor Manufacturing Company Ltd.
发明人： Oscar M.K. Law , Kuo H. Wu
IPC分类号： H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/16 , H01L2225/06541 , H01L2924/00013 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/13099 , H01L2224/05552
摘要： A system and method for making semiconductor die connections with through-silicon vias (TSVs) are disclosed. A semiconductor die is manufactured with both via-first TSVs as well as via-last TSVs in order to establish low resistance paths for die connections between adjacent dies as well as for providing a low resistance path for feedthrough channels between multiple dies.
摘要翻译：公开了一种用于通过硅通孔（TSV）制造半导体管芯连接的系统和方法。制造半导体管芯，其具有通孔第一TSV以及通孔最终TSV，以便建立用于相邻管芯之间的管芯连接的低电阻路径，以及为多个管芯之间的穿通通道提供低电阻路径。

5. 发明申请

US20140264941A1 Three-Dimensional Semiconductor Architecture 审中-公开
标题翻译：三维半导体架构
公开(公告)号：US20140264941A1
公开(公告)日：2014-09-18
申请号：US14290687
申请日：2014-05-29
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oscar M. K. Law , Kuo H. Wu
IPC分类号： H01L23/525
CPC分类号： H01L21/76898 , H01L21/768 , H01L21/76877 , H01L21/8221 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/5286 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/83 , H01L25/0657 , H01L27/0688 , H01L27/1203 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/05552
摘要： A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
摘要翻译：公开了一种用于制造具有贯穿衬底通孔的半导体管芯连接的系统和方法。通过衬底通孔形成穿过衬底以允许信号连接以及电源和接地连接。在一个实施例中，衬底具有围绕内部区域的内部区域和周边区域。第一组通过衬底通孔位于外围区域内，并且第二组通过衬底通孔位于内部区域内，其中第二组通过衬底通孔是功率矩阵的一部分。第二组贯通衬底通孔将衬底平分成第一部分和第二部分。

6. 发明授权

US09559003B2 Three-dimensional semiconductor architecture 有权
标题翻译：三维半导体架构
公开(公告)号：US09559003B2
公开(公告)日：2017-01-31
申请号：US14827749
申请日：2015-08-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oscar M. K. Law , Kuo H. Wu
IPC分类号： H01L21/768 , H01L23/00 , H01L23/48 , H01L23/525 , H01L23/528 , H01L25/065 , H01L23/498 , H01L21/822 , H01L27/06 , H01L27/12
CPC分类号： H01L21/76898 , H01L21/768 , H01L21/76877 , H01L21/8221 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/5286 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/83 , H01L25/0657 , H01L27/0688 , H01L27/1203 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/05552
摘要： A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
摘要翻译：公开了一种用于制造具有贯穿衬底通孔的半导体管芯连接的系统和方法。通过衬底通孔形成穿过衬底以允许信号连接以及电源和接地连接。在一个实施例中，衬底具有围绕内部区域的内部区域和周边区域。第一组通过衬底通孔位于外围区域内，并且第二组通过衬底通孔位于内部区域内，其中第二组通过衬底通孔是功率矩阵的一部分。第二组贯通衬底通孔将衬底平分成第一部分和第二部分。

7. 发明申请

US20150357240A1 Three-Dimensional Semiconductor Architecture 审中-公开
标题翻译：三维半导体架构
公开(公告)号：US20150357240A1
公开(公告)日：2015-12-10
申请号：US14827749
申请日：2015-08-17
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oscar M. K. Law , Kuo H. Wu
IPC分类号： H01L21/768 , H01L23/00
CPC分类号： H01L21/76898 , H01L21/768 , H01L21/76877 , H01L21/8221 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/5286 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/83 , H01L25/0657 , H01L27/0688 , H01L27/1203 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/05552
摘要： A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
摘要翻译：公开了一种用于制造具有贯穿衬底通孔的半导体管芯连接的系统和方法。通过衬底通孔形成穿过衬底以允许信号连接以及电源和接地连接。在一个实施例中，衬底具有围绕内部区域的内部区域和周边区域。第一组通过衬底通孔位于外围区域内，并且第二组通过衬底通孔位于内部区域内，其中第二组通过衬底通孔是功率矩阵的一部分。第二组贯通衬底通孔将衬底平分成第一部分和第二部分。

8. 发明授权

US09111936B2 Three-dimensional semiconductor architecture 有权
标题翻译：三维半导体架构
公开(公告)号：US09111936B2
公开(公告)日：2015-08-18
申请号：US14290687
申请日：2014-05-29
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Oscar M. K. Law , Kuo H. Wu
IPC分类号： H01L23/528 , H01L23/48 , H01L23/525 , H01L23/00 , H01L25/065 , H01L21/768 , H01L23/498 , H01L21/822 , H01L27/06 , H01L27/12
CPC分类号： H01L21/76898 , H01L21/768 , H01L21/76877 , H01L21/8221 , H01L23/481 , H01L23/49827 , H01L23/525 , H01L23/5286 , H01L24/05 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/83 , H01L25/0657 , H01L27/0688 , H01L27/1203 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/13 , H01L2224/13009 , H01L2224/13025 , H01L2224/13099 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/14 , H01L2924/15311 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/05552
摘要： A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.
摘要翻译：公开了一种用于制造具有贯穿衬底通孔的半导体管芯连接的系统和方法。通过衬底通孔形成穿过衬底以允许信号连接以及电源和接地连接。在一个实施例中，衬底具有围绕内部区域的内部区域和周边区域。第一组通过衬底通孔位于外围区域内，并且第二组通过衬底通孔位于内部区域内，其中第二组通过衬底通孔是功率矩阵的一部分。第二组贯通衬底通孔将衬底平分成第一部分和第二部分。

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