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1. 发明申请

US20150079752A1 FinFET Design Controlling Channel Thickness 审中-公开
标题翻译： FinFET设计控制通道厚度
公开(公告)号：US20150079752A1
公开(公告)日：2015-03-19
申请号：US14541050
申请日：2014-11-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Zhiqiang Wu , Ken-Ichi Goto , Wen-Hsing Hsieh , Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang
IPC分类号： H01L21/02 , H01L29/66
CPC分类号： H01L21/02362 , H01L21/02123 , H01L21/02293 , H01L21/0234 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
摘要翻译：用于控制通道厚度并防止由于形成小特征而引起的变化的系统和方法。一个实施例包括在衬底上升起的翅片，并且在翅片上形成覆盖层。通道载体从重掺杂的翅片排斥并限制在封盖层内。这形成了允许对栅极进行更大静电控制的薄通道。

2. 发明公开

US20230164970A1 MEMORY DEVICES INCLUDING TRANSISTORS ON MULTIPLE LAYERS 审中-公开
公开(公告)号：US20230164970A1
公开(公告)日：2023-05-25
申请号：US17743233
申请日：2022-05-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ken-Ichi Goto , Cheng-Yi Wu
IPC分类号： H01L27/11 , H01L29/786 , H01L23/528 , H01L29/66 , H01L21/8234
CPC分类号： H01L27/1108 , H01L29/7869 , H01L29/78618 , H01L23/5283 , H01L29/66742 , H01L21/823431 , H01L21/823418
摘要： A semiconductor device including a substrate, a first layer over the substrate, and a second layer over the first layer. The first layer including a first fin structure, a first gate structure that overlaps the first fin structure to form a first pass-gate transistor, and a second gate structure that is separate from the first gate structure and that overlaps the first fin structure to form a first pull-down transistor. The second layer including a third gate structure disposed over the second gate structure and connected to the second gate structure, a first semiconductor oxide structure disposed on the third gate structure, and a first drain/source region and a second drain/source region disposed on the first semiconductor oxide structure, wherein the third gate structure, the first semiconductor oxide structure, the first drain/source region, and the second drain/source region constitute a first pull-up transistor.

3. 发明授权

US10985246B2 MOSFET with selective dopant deactivation underneath gate 有权
公开(公告)号：US10985246B2
公开(公告)日：2021-04-20
申请号：US16202796
申请日：2018-11-28
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
IPC分类号： H01L29/66 , H01L29/10 , H01L29/78 , H01L29/16 , H01L21/265
摘要： A semiconductor device includes a channel region comprising dopants, a gate structure over the channel region and a deactivated region underneath the gate structure and partially within the channel region. Dopants within the deactivated region are deactivated. The deactivated region includes carbon. The deactivated region is physically separated from a top surface of a substrate by a portion of the substrate that is free of carbon.

4. 发明授权

US09318322B2 FinFET design controlling channel thickness 有权
标题翻译： FinFET设计控制通道厚度
公开(公告)号：US09318322B2
公开(公告)日：2016-04-19
申请号：US14541050
申请日：2014-11-13
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Zhiqiang Wu , Ken-Ichi Goto , Wen-Hsing Hsieh , Jon-Hsu Ho , Chih-Ching Wang , Ching-Fang Huang
IPC分类号： H01L21/336 , H01L29/78 , H01L29/36 , H01L21/02 , H01L29/66 , H01L29/10
CPC分类号： H01L21/02362 , H01L21/02123 , H01L21/02293 , H01L21/0234 , H01L29/1054 , H01L29/66795 , H01L29/785
摘要： System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.
摘要翻译：用于控制通道厚度并防止由于形成小特征而引起的变化的系统和方法。一个实施例包括在衬底上升起的翅片，并且在翅片上形成覆盖层。通道载体从重掺杂的翅片排斥并限制在封盖层内。这形成了允许对栅极进行更大静电控制的薄通道。

5. 发明申请

US20130137236A1 Tunnel Field-Effect Transistor with Narrow Band-Gap Channel and Strong Gate Coupling 有权
公开(公告)号：US20130137236A1
公开(公告)日：2013-05-30
申请号：US13741086
申请日：2013-01-14
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Krishna Kumar Bhuwalka , Ken-Ichi Goto
IPC分类号： H01L29/66
CPC分类号： H01L29/66545 , H01L29/66356 , H01L29/7391
摘要： A semiconductor device and the methods of forming the same are provided. The semiconductor device includes a low energy band-gap layer comprising a semiconductor material; a gate dielectric on the low energy band-gap layer; a gate electrode over the gate dielectric; a first source/drain region adjacent the gate dielectric, wherein the first source/drain region is of a first conductivity type; and a second source/drain region adjacent the gate dielectric. The second source/drain region is of a second conductivity type opposite the first conductivity type. The low energy band-gap layer is located between the first and the second source/drain regions.

6. 发明申请

US20140024182A1 Non-Uniform Channel Junction-Less Transistor 有权
标题翻译：非均匀通道无结晶体管
公开(公告)号：US20140024182A1
公开(公告)日：2014-01-23
申请号：US13941199
申请日：2013-07-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ken-Ichi Goto , Zhiqiang Wu
IPC分类号： H01L29/66
CPC分类号： H01L29/66803 , G01N33/6893 , H01L29/785 , H01L2029/7857
摘要： The present disclosure discloses a method of forming a semiconductor layer on a substrate. The method includes patterning the semiconductor layer into a fin structure. The method includes forming a gate dielectric layer and a gate electrode layer over the fin structure. The method includes patterning the gate dielectric layer and the gate electrode layer to form a gate structure in a manner so that the gate structure wraps around a portion of the fin structure. The method includes performing a plurality of implantation processes to form source/drain regions in the fin structure. The plurality of implantation processes are carried out in a manner so that a doping profile across the fin structure is non-uniform, and a first region of the portion of the fin structure that is wrapped around by the gate structure has a lower doping concentration level than other regions of the fin structure.
摘要翻译：本公开公开了一种在衬底上形成半导体层的方法。该方法包括将半导体层图案化成翅片结构。该方法包括在鳍结构上形成栅介电层和栅电极层。该方法包括以栅极结构缠绕翅片结构的一部分的方式构图栅极电介质层和栅极电极层以形成栅极结构。该方法包括执行多个注入工艺以在散热片结构中形成源极/漏极区域。多个注入工艺以这样一种方式进行，使得跨鳍片结构的掺杂分布不均匀，鳍结构部分被栅极结构缠绕的部分的第一区域具有较低的掺杂浓度水平比其他地区的鳍结构。

7. 发明申请

US20220246678A1 SPACER-DEFINED BACK-END TRANSISTOR AS MEMORY SELECTOR 有权
公开(公告)号：US20220246678A1
公开(公告)日：2022-08-04
申请号：US17718481
申请日：2022-04-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ken-Ichi Goto , Chung-Te Lin , Mauricio Manfrini
IPC分类号： H01L27/22 , H01L27/24
摘要： The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device comprises a substrate and a lower interconnect metal layer disposed over the substrate. A selecting transistor is disposed over the lower interconnect metal layer. A memory cell is disposed over the selecting transistor and comprises a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.

8. 发明授权

US12068374B2 Method of dopant deactivation underneath gate 有权
公开(公告)号：US12068374B2
公开(公告)日：2024-08-20
申请号：US17229206
申请日：2021-04-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Ken-Ichi Goto , Wei-Hao Wu , Yuan-Chen Sun , Zhiqiang Wu
IPC分类号： H01L29/10 , H01L29/16 , H01L29/66 , H01L29/78 , H01L21/265
CPC分类号： H01L29/1041 , H01L29/1045 , H01L29/1608 , H01L29/66537 , H01L29/66651 , H01L29/7833 , H01L21/26506 , H01L21/2658 , H01L29/66545
摘要： A method of fabricating a device on a substrate includes doping a channel region of the device with dopants. The method further includes growing an undoped epitaxial layer over the channel region, wherein growing the undoped epitaxial layer comprises deactivating dopants in the channel region to form a deactivated region. The method further includes forming a gate structure over the deactivated region.

9. 发明公开

US20240136441A1 SEMICONDUCTOR DEVICE AND MEHTOD OF FABRICATING THE SAME 审中-公开
公开(公告)号：US20240136441A1
公开(公告)日：2024-04-25
申请号：US18164600
申请日：2023-02-05
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ken-Ichi Goto , Cheng-Yi Wu
IPC分类号： H01L29/786 , H01L21/02 , H01L27/12 , H01L29/04 , H01L29/49 , H01L29/66
CPC分类号： H01L29/78684 , H01L21/02488 , H01L21/02491 , H01L21/02502 , H01L21/02516 , H01L21/02521 , H01L21/02532 , H01L21/02565 , H01L21/02598 , H01L21/02609 , H01L27/1207 , H01L27/1225 , H01L27/1229 , H01L27/1237 , H01L29/045 , H01L29/4908 , H01L29/66742 , H01L29/66969 , H01L29/78681 , H01L29/7869 , H01L29/18
摘要： A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is or . The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

10. 发明授权

US10157985B2 MOSFET with selective dopant deactivation underneath gate 有权
公开(公告)号：US10157985B2
公开(公告)日：2018-12-18
申请号：US14855477
申请日：2015-09-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Dhanyakumar Mahaveer Sathaiya , Kai-Chieh Yang , Wei-Hao Wu , Ken-Ichi Goto , Zhiqiang Wu , Yuan-Chen Sun
IPC分类号： H01L29/10 , H01L29/66 , H01L29/78 , H01L29/16 , H01L21/265
摘要： A metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a channel region comprising dopants of a first type. The MOSFET device further includes a gate dielectric over the channel region, and a gate over the gate dielectric. The MOSFET device further includes a source comprising dopants of a second type, and a drain comprising dopants of the second type, wherein the channel region is between the source and the drain. The MOSFET device further includes a deactivated region underneath the gate, wherein dopants within the deactivated region are deactivated.

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