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1. 发明申请

US20140205938A1 EUV Mask and Method for Forming the Same 有权
标题翻译： EUV掩模及其形成方法
公开(公告)号：US20140205938A1
公开(公告)日：2014-07-24
申请号：US14245642
申请日：2014-04-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Fang Yu , Ting-Hao Hsu , Sheng-Chi Chin
IPC分类号： G03F1/46
CPC分类号： G03F1/46 , B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/54 , G03F1/58
摘要： An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.
摘要翻译：极光紫外（EUV）掩模可以用在光刻中，例如用于制造半导体晶片的方法。 EUV掩模包括低热膨胀材料（LTEM）基板和设置在其上的反射多层（ML）。覆盖层设置在反射ML上，并且设置在覆盖层上的图案化吸收层。该图案包括抗反射（ARC）型图案。

2. 发明授权

US09152035B2 Lithographic photomask with inclined sides 有权
标题翻译：平面光栅与倾斜的边
公开(公告)号：US09152035B2
公开(公告)日：2015-10-06
申请号：US14051942
申请日：2013-10-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Fang Yu , Ting-Hao Hsu , Sheng-Chi Chin
IPC分类号： G03F1/22 , G03F1/24
CPC分类号： G03F1/22
摘要： A lithographic process will use a mask or photomask. The photomask includes a first material layer, the first material layer providing a first outer surface of the photomask. The photomask also includes a second material layer over the first material layer, the second material layer providing a second outer surface of the photomask. The two outer surfaces are substantially in parallel and a distance between the two outer surfaces along a first axis perpendicular to the two outer surfaces defines a thickness of the photomask. Also, the two outer surfaces are connected by a plurality of sides, at least one of the sides is not perpendicular to the two outer surfaces and the at least one of the sides provides substantial area for holding the lithographic photomask.
摘要翻译：光刻工艺将使用掩模或光掩模。光掩模包括第一材料层，第一材料层提供光掩模的第一外表面。光掩模还包括在第一材料层上的第二材料层，第二材料层提供光掩模的第二外表面。两个外表面基本上是平行的，沿垂直于两个外表面的第一轴线的两个外表面之间的距离限定了光掩模的厚度。此外，两个外表面通过多个侧面连接，至少一个侧面不垂直于两个外表面，并且至少一个侧面提供用于保持光刻光掩模的实质区域。

3. 发明申请

US20160274471A1 PELLICLE AGING ESTIMATION AND PARTICLE REMOVAL FROM PELLICLE VIA ACOUSTIC WAVES 有权
标题翻译：通过声音波形从胶囊中分离出的细胞衰老估计和颗粒
公开(公告)号：US20160274471A1
公开(公告)日：2016-09-22
申请号：US14658399
申请日：2015-03-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Sheng-Chi Chin , Ting-Hao Hsu , Mark Chang
IPC分类号： G03F7/20
CPC分类号： G03F1/84 , G03F1/62
摘要： A pellicle is disposed over a lithography mask. An acoustic wave generator is placed over the pellicle. The acoustic wave generator is configured to generate acoustic waves to cause the pellicle to vibrate at a target resonance frequency. A resonance detection tool is configured to detect an actual resonance frequency of the pellicle in response to the acoustic waves. One or more electronic processors are configured to estimate an age condition of the pellicle as a function of a shift of the actual resonance frequency from the target resonance frequency.
摘要翻译：防护薄膜组件设置在光刻掩模上。声波发生器放置在防护薄膜上。声波发生器被配置为产生声波以使防护薄膜以目标谐振频率振动。谐振检测工具被配置为响应于声波来检测防护薄膜的实际谐振频率。一个或多个电子处理器被配置为根据实际谐振频率与目标共振频率的偏移来估计防护薄膜的年龄条件。

4. 发明授权

US09354510B2 EUV mask and method for forming the same 有权
标题翻译： EUV掩模及其形成方法
公开(公告)号：US09354510B2
公开(公告)日：2016-05-31
申请号：US14245642
申请日：2014-04-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Fang Yu , Ting-Hao Hsu , Sheng-Chi Chin
IPC分类号： G03F1/24 , G03F1/46 , G03F1/54 , G03F1/58 , B82Y10/00 , B82Y40/00
CPC分类号： G03F1/46 , B82Y10/00 , B82Y40/00 , G03F1/24 , G03F1/54 , G03F1/58
摘要： An extreme ultraviolet (EUV) mask can be used in lithography, such as is used in the fabrication of a semiconductor wafer. The EUV mask includes a low thermal expansion material (LTEM) substrate and a reflective multilayer (ML) disposed thereon. A capping layer is disposed on the reflective ML and a patterned absorption layer disposed on the capping layer. The pattern includes an antireflection (ARC) type pattern.
摘要翻译：极光紫外（EUV）掩模可以用在光刻中，例如用于制造半导体晶片的方法。 EUV掩模包括低热膨胀材料（LTEM）基板和设置在其上的反射多层（ML）。覆盖层设置在反射ML上，并且设置在覆盖层上的图案化吸收层。该图案包括抗反射（ARC）型图案。

5. 发明申请

US20190072849A1 Pellicle for Advanced Lithography 审中-公开
公开(公告)号：US20190072849A1
公开(公告)日：2019-03-07
申请号：US16181637
申请日：2018-11-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Ting-Hao Hsu , Ching-Hsiang Chang , Sheng-Chi Chin
IPC分类号： G03F1/64 , G03F7/20
CPC分类号： G03F1/64 , G03F7/2004
摘要： Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.

6. 发明授权

US10126644B2 Pellicle for advanced lithography 有权
公开(公告)号：US10126644B2
公开(公告)日：2018-11-13
申请号：US15019478
申请日：2016-02-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Ting-Hao Hsu , Ching-Hsiang Chang , Sheng-Chi Chin
IPC分类号： G03F1/62 , G03F1/64 , G03F7/20
摘要： The present disclosure provides an apparatus for a semiconductor lithography process in accordance with some embodiments. The apparatus includes a pellicle membrane, a pellicle frame attached to the pellicle membrane. The pellicle frame has a surface that defines at least one groove. The apparatus further includes a substrate that is in contact with the surface of the pellicle frame such that the grove is positioned between the pellicle frame and the substrate.

7. 发明申请

US20150104731A1 Lithographic Photomask With Inclined Sides 有权
标题翻译：带斜面的平版光掩模
公开(公告)号：US20150104731A1
公开(公告)日：2015-04-16
申请号：US14051942
申请日：2013-10-11
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Fang Yu , Ting-Hao Hsu , Sheng-Chi Chin
IPC分类号： G03F1/22
CPC分类号： G03F1/22
摘要： A lithographic process will use a mask or photomask. The photomask includes a first material layer, the first material layer providing a first outer surface of the photomask. The photomask also includes a second material layer over the first material layer, the second material layer providing a second outer surface of the photomask. The two outer surfaces are substantially in parallel and a distance between the two outer surfaces along a first axis perpendicular to the two outer surfaces defines a thickness of the photomask. Also, the two outer surfaces are connected by a plurality of sides, at least one of the sides is not perpendicular to the two outer surfaces and the at least one of the sides provides substantial area for holding the lithographic photomask.
摘要翻译：光刻工艺将使用掩模或光掩模。光掩模包括第一材料层，第一材料层提供光掩模的第一外表面。光掩模还包括在第一材料层上的第二材料层，第二材料层提供光掩模的第二外表面。两个外表面基本上是平行的，沿垂直于两个外表面的第一轴线的两个外表面之间的距离限定了光掩模的厚度。此外，两个外表面通过多个侧面连接，至少一个侧面不垂直于两个外表面，并且至少一个侧面提供用于保持光刻光掩模的实质区域。

8. 发明申请

US20150099364A1 METHOD FOR INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：集成电路制造方法
公开(公告)号：US20150099364A1
公开(公告)日：2015-04-09
申请号：US14045963
申请日：2013-10-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Fang Yu , Ting-Hao Hsu , Chia-Ching Huang
IPC分类号： H01L21/263
CPC分类号： H01L21/3086 , G03F7/203 , G03F7/70433 , G03F7/70466 , H01L21/0274 , H01L21/2633 , H01L21/3088
摘要： Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
摘要翻译：提供了一种集成电路（IC）制造方法。所述方法包括接收掩模，所述掩模具有多个管芯并接收晶片，所述晶片具有抗蚀剂层。该方法还包括使用掩模以分数辐射剂量曝光抗蚀剂层，从而形成第一多个图像; 将掩模相对于晶片重新定位; 并用另一分数辐射剂量使用掩模曝光抗蚀剂层。形成第二多个图像，其中第二多个图像的一部分叠加在第一多个图像的另一部分上。

9. 发明授权

US08980108B1 Method for integrated circuit fabrication 有权
标题翻译：集成电路制造方法
公开(公告)号：US08980108B1
公开(公告)日：2015-03-17
申请号：US14045963
申请日：2013-10-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Fang Yu , Ting-Hao Hsu , Chia-Ching Huang
IPC分类号： H01B13/00 , H01L21/263
CPC分类号： H01L21/3086 , G03F7/203 , G03F7/70433 , G03F7/70466 , H01L21/0274 , H01L21/2633 , H01L21/3088
摘要： Provided is an integrated circuit (IC) fabrication method. The method includes receiving a mask, the mask having a plurality of dies and receiving a wafer, the wafer having a resist layer. The method further includes exposing the resist layer using the mask with a fraction radiation dose thereby forming a first plurality of images; re-positioning the mask relative to the wafer; and exposing the resist layer using the mask with another fraction radiation dose. A second plurality of images is formed, wherein a portion of the second plurality of images is superimposed over another portion of the first plurality of images.
摘要翻译：提供了一种集成电路（IC）制造方法。所述方法包括接收掩模，所述掩模具有多个管芯并接收晶片，所述晶片具有抗蚀剂层。该方法还包括使用掩模以分数辐射剂量曝光抗蚀剂层，从而形成第一多个图像; 将掩模相对于晶片重新定位; 并用另一分数辐射剂量使用掩模曝光抗蚀剂层。形成第二多个图像，其中第二多个图像的一部分叠加在第一多个图像的另一部分上。

10. 发明授权

US10691017B2 Pellicle for advanced lithography 有权
公开(公告)号：US10691017B2
公开(公告)日：2020-06-23
申请号：US16181637
申请日：2018-11-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Ching Lee , Ching-Fang Yu , Chun-Hung Lin , Ting-Hao Hsu , Ching-Hsiang Chang , Sheng-Chi Chin
IPC分类号： G03F1/64 , G03F7/20
摘要： Pellicle-mask systems for advanced lithography, such as extreme ultraviolet lithography, are disclosed herein. An exemplary pellicle-mask system includes a mask having an integrated circuit (IC) pattern, a pellicle membrane, and a pellicle frame. The pellicle frame has a first surface attached to the pellicle membrane and a second surface opposite the first surface attached to the mask, such that the IC pattern of the mask is positioned within an enclosed space defined by the mask, the pellicle membrane, and the pellicle frame. A void is defined between the pellicle frame and the mask, where the void is defined by a portion of the second surface of the pellicle membrane not attached to the mask. The void is not in communication with the enclosed space and is not in communication with an exterior space of the pellicle-mask system.

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