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1. 发明申请

US20210366844A1 VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION 有权
公开(公告)号：US20210366844A1
公开(公告)日：2021-11-25
申请号：US17393619
申请日：2021-08-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Kam-Tou Sio , Chih-Ming Lai , Chun-Kuang Chen , Chih-Liang Chen , Charles Chew-Yuen Young , Chi-Yeh Yu , Jiann-Tyng Tzeng , Ru-Gun Liu , Wen-Hao Chen
IPC分类号： H01L23/00 , H01L23/528 , H01L23/522 , H01L23/485
摘要： The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.

2. 发明申请

US20210366726A1 Via Connection to a Partially Filled Trench 有权
公开(公告)号：US20210366726A1
公开(公告)日：2021-11-25
申请号：US17397756
申请日：2021-08-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shih-Ming Chang , Chih-Ming Lai , Ru-Gun Liu , Tsai-Sheng Gau , Chung-Ju Lee , Tien-I Bao , Shau-Lin Shue
IPC分类号： H01L21/321 , H01L21/768 , H01L21/311 , H01L21/3105 , H01L23/522
摘要： An integrated circuit structure includes a first metal feature formed into a first dielectric layer, a second metal feature formed into a second dielectric layer, the second dielectric layer being disposed on said first dielectric layer, and a via connecting the first metal feature to the second metal feature, wherein a top portion of the via is offset from a bottom portion of the via.

3. 发明授权

US10977421B2 System for and method of manufacturing an integrated circuit 有权
公开(公告)号：US10977421B2
公开(公告)日：2021-04-13
申请号：US16793693
申请日：2020-02-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Wei-Cheng Lin , Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Shih-Wei Peng , Wei-Chen Chien
IPC分类号： G06F30/30 , G06F30/398 , G06F30/392
摘要： A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.

4. 发明授权

US10714485B2 Semiconductor device which includes Fins 有权
公开(公告)号：US10714485B2
公开(公告)日：2020-07-14
申请号：US16126875
申请日：2018-09-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Liang Chen , Chih-Ming Lai , Charles Chew-Yuen Young , Chin-Yuan Tseng , Jiann-Tyng Tzeng , Kam-Tou Sio , Ru-Gun Liu , Wei-Liang Lin , L. C. Chou
IPC分类号： H01L27/11 , H01L21/8234 , H01L27/088 , H01L21/308 , H01L29/78 , H01L29/66 , H01L21/311
摘要： A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.

5. 发明授权

US10665467B2 Spacer etching process for integrated circuit design 有权
公开(公告)号：US10665467B2
公开(公告)日：2020-05-26
申请号：US15357203
申请日：2016-11-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ru-Gun Liu , Cheng-Hsiung Tsai , Chung-Ju Lee , Chih-Ming Lai , Chia-Ying Lee , Jyu-Horng Shieh , Ken-Hsien Hsieh , Ming-Feng Shieh , Shau-Lin Shue , Shih-Ming Chang , Tien-I Bao , Tsai-Sheng Gau
IPC分类号： H01L21/308 , H01L21/8234 , H01L21/033 , H01L21/311 , H01L21/768 , H01L21/02 , H01L21/027 , H01L21/3105
摘要： A method includes forming a first layer on a substrate; forming a first plurality of trenches in the first layer by a first patterning process; and forming a second plurality of trenches in the first layer by second patterning process, wherein a first trench of the second plurality merges with two trenches of the first plurality to form a continuous trench. The method further includes forming spacer features on sidewalls of the first and second pluralities of trenches. The spacer features have a thickness. A width of the first trench is equal to or less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench.

6. 发明申请

US20180138042A1 Methods for Integrated Circuit Design and Fabrication 审中-公开
公开(公告)号：US20180138042A1
公开(公告)日：2018-05-17
申请号：US15852129
申请日：2017-12-22
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsong-Hua Ou , Ken-Hsien Hsieh , Shih-Ming Chang , Wen-Chun Huang , Chih-Ming Lai , Ru-Gun Liu , Tsai-Sheng Gau
IPC分类号： H01L21/033 , H01L21/027 , H01L21/3213 , H01L21/311 , H01L21/321
CPC分类号： H01L21/0338 , H01L21/0274 , H01L21/0335 , H01L21/0337 , H01L21/31144 , H01L21/3212 , H01L21/32139
摘要： The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

7. 发明授权

US09852908B2 Methods for integrated circuit design and fabrication 有权
公开(公告)号：US09852908B2
公开(公告)日：2017-12-26
申请号：US15174131
申请日：2016-06-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsong-Hua Ou , Ken-Hsien Hsieh , Shih-Ming Chang , Wen-Chun Huang , Chih-Ming Lai , Ru-Gun Liu , Tsai-Sheng Gau
IPC分类号： H01L21/033 , H01L21/027 , H01L21/321 , H01L21/311 , H01L21/3213
CPC分类号： H01L21/0338 , H01L21/0274 , H01L21/0335 , H01L21/0337 , H01L21/31144 , H01L21/3212 , H01L21/32139
摘要： The present disclosure provides a method of patterning a target material layer over a semiconductor substrate. The method includes steps of forming a spacer feature over the target material layer using a first sub-layout and performing a photolithographic patterning process using a second sub-layout to form a first feature. A portion of the first feature extends over the spacer feature. The method further includes steps of removing the portion of the first feature extending over the spacer feature and removing the spacer feature. Other methods and associated patterned semiconductor wafers are also provided herein.

8. 发明授权

US09627262B2 Method of patterning features of a semiconductor device 有权
公开(公告)号：US09627262B2
公开(公告)日：2017-04-18
申请号：US14698094
申请日：2015-04-28
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wei-Chao Chiu , Chen-Yu Chen , Chih-Ming Lai , Ming-Feng Shieh , Nian-Fuh Cheng , Ru-Gun Liu , Wen-Chun Huang
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/308 , H01L29/66 , H01L29/78 , H01L21/02 , H01L21/306 , H01L21/311
CPC分类号： H01L21/823431 , H01L21/02238 , H01L21/02255 , H01L21/30604 , H01L21/308 , H01L21/3086 , H01L21/31111 , H01L21/31144 , H01L29/6656 , H01L29/66795 , H01L29/785
摘要： A method of semiconductor device fabrication including forming a mandrel on a semiconductor substrate is provided. The method continues to include oxidizing a region the mandrel to form an oxidized region, wherein the oxidized region abuts a sidewall of the mandrel. The mandrel is then removed from the semiconductor substrate. After removing the mandrel, the oxidized region is used to pattern an underlying layer formed on the semiconductor substrate.

9. 发明申请

US20160284591A1 SELF-ALIGNED SEMICONDUCTOR FABRICATION WITH FOSSE FEATURES 审中-公开
标题翻译：具有FOSSE特性的自对准半导体制造
公开(公告)号：US20160284591A1
公开(公告)日：2016-09-29
申请号：US15174699
申请日：2016-06-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shih-Ming Chang , Ken-Hsien Hsieh , Chih-Ming Lai , Ming-Feng Shieh , Ru-Gun Liu , Tsai-Sheng Gau
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31111 , H01L21/31144 , H01L21/32133 , H01L21/32139 , H01L21/76897 , H01L23/5226 , H01L23/5283
摘要： The present disclosure describes methods for transferring a desired layout into a target layer on a semiconductor substrate. An embodiment of the methods includes forming a first desired layout feature as a first line over the target layer; forming a spacer around the first line; depositing a spacer-surrounding material layer; removing the spacer to form a fosse pattern trench surrounding the first line; and transferring the fosse pattern trench into the target layer to form a fosse feature trench in the target layer, wherein the fosse feature trench surrounds a first portion of the target layer that is underneath a protection layer. In some embodiments, the method further includes patterning a second desired layout feature of the desired layout into the target layer wherein the fosse feature trench and the protection layer serve to self-align the second desired layout feature with the first portion of the target layer.
摘要翻译：本公开描述了将期望的布局转移到半导体衬底上的目标层中的方法。所述方法的一个实施例包括在目标层上形成第一期望布局特征作为第一行; 在第一条线周围形成间隔物; 沉积间隔物周围的材料层; 去除所述间隔物以形成围绕所述第一线的顶点图案沟槽; 以及将所述花纹图案沟槽转移到所述目标层中，以在所述目标层中形成顶点特征沟槽，其中所述特征沟槽围绕所述目标层的位于保护层下方的第一部分。在一些实施例中，该方法还包括将期望布局的第二所需布局特征图案化成目标层，其中，所述优点特征沟槽和所述保护层用于使所述第二期望布局特征与所述目标层的所述第一部分自对准。

10. 发明授权

US09449880B1 Fin patterning methods for increased process margin 有权
标题翻译：翅片图案化方法增加工艺余量
公开(公告)号：US09449880B1
公开(公告)日：2016-09-20
申请号：US14632979
申请日：2015-02-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chin-Yuan Tseng , Chi-Cheng Hung , Chun-Kuang Chen , Chih-Ming Lai , Huan-Just Lin , Ru-Gun Liu , Tsai-Sheng Gau , Wei-Liang Lin
IPC分类号： H01L21/311 , H01L21/8234 , H01L29/66 , H01L21/308
CPC分类号： H01L21/823431 , H01L21/3086 , H01L29/6653 , H01L29/6656
摘要： A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成多个第一间隔物。多个第二间隔物的第二间隔物沉积在每个第一间隔物的侧壁上。在一些实施例中，相邻的第一间隔件之间的间隔被配置为使得形成在相邻的第一间隔件的侧壁上的第二间隔物物理地合并以形成合并的第二间隔件。可以执行第二间隔切割工艺以选择性地去除至少一个第二间隔物。在一些实施例中，多个第三间隔件的第三间隔件形成在每个第二间隔件的侧壁上。可以执行第三间隔切割工艺以选择性地去除至少一个第三间隔物。在衬底上执行第一蚀刻工艺以形成鳍片区域。在第一蚀刻工艺期间，多个第三间隔物掩盖衬底的部分。

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