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1. 发明公开

US20240363722A1 AIR SPACER FORMATION WITH A SPIN-ON DIELECTRIC MATERIAL 审中-公开
公开(公告)号：US20240363722A1
公开(公告)日：2024-10-31
申请号：US18769246
申请日：2024-07-10
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ting-Ting CHEN , Tsai-Jung Ho , Tsung-Han Ko , Tetsuji Ueno , Yahru Cheng , Chen-Han Wang , Keng-Chu Lin , Shuen-Shin Liang , Tsu-Hsiu Perng
IPC分类号： H01L29/49 , H01L29/06 , H01L29/66
CPC分类号： H01L29/4991 , H01L29/0653 , H01L29/6656
摘要： The present disclosure describes a method of forming an intermediate spacer structure between a gate structure and a source/drain (S/D) contact structure and removing a top portion of the intermediate spacer structure to form a recess. The intermediate spacer structure includes a first spacer layer, a second spacer layer, and a sacrificial spacer layer between the first spacer layer and the second spacer layer. The method further includes removing the sacrificial spacer layer to form an air gap between the first spacer layer and the second spacer layer and spinning a dielectric layer on the air gap, the first spacer layer, and the second spacer layer to fill in the recess and seal the air gap. The dielectric layer includes raw materials for a spin-on dielectric material.

2. 发明授权

US11257753B2 Interconnect structure and method for manufacturing the interconnect structure 有权
公开(公告)号：US11257753B2
公开(公告)日：2022-02-22
申请号：US16884925
申请日：2020-05-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Khaderbad Mrunal Abhijith , Yu-Yun Peng , Fu-Ting Yen , Chen-Han Wang , Tsu-Hsiu Perng , Keng-Chu Lin
IPC分类号： H01L23/522 , H01L23/532 , H01L21/768
摘要： The present disclosure provides an interconnect structure, including a substrate having a conductive region adjacent to a gate region, a contact over the conductive region, a first interlayer dielectric layer (ILD) surrounding the contact, a via over the contact, a first densified dielectric layer surrounding the via, wherein the densified dielectric layer has a first density, and a second ILD layer over the first ILD layer and surrounding the via, wherein the second ILD layer has a second density, the first density is greater than a second density.

3. 发明授权

US11735666B2 Gate all around structure with additional silicon layer and method for forming the same 有权
公开(公告)号：US11735666B2
公开(公告)日：2023-08-22
申请号：US17814881
申请日：2022-07-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chen-Han Wang , Pei-Hsun Wang , Chun-Hsiung Lin , Chih-Hao Wang
IPC分类号： H01L29/78 , H01L21/02 , H01L29/08 , H01L29/06 , H01L29/66
CPC分类号： H01L29/785 , H01L21/02532 , H01L21/02554 , H01L21/02603 , H01L29/0669 , H01L29/0847 , H01L29/66795
摘要： Methods for manufacturing a semiconductor structure are provided. The semiconductor structure includes a substrate a substrate and channel layers vertically stacked over the substrate. The semiconductor structure also includes a dielectric fin structure formed adjacent to the channel layers and a gate structure abutting the channel layers and the dielectric fin structure. The semiconductor structure also includes a source/drain structure attached to the channel layers and a contact formed over the source/drain structure. The semiconductor structure also includes a Si layer covering a portion of a top surface of the source/drain structure. In addition, the Si layer is sandwiched between the dielectric fin structure and the contact.

4. 发明授权

US12119404B2 Gate all around structure with additional silicon layer and method for forming the same 有权
公开(公告)号：US12119404B2
公开(公告)日：2024-10-15
申请号：US18344057
申请日：2023-06-29
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chen-Han Wang , Pei-Hsun Wang , Chun-Hsiung Lin , Chih-Hao Wang
IPC分类号： H01L29/78 , H01L21/02 , H01L29/06 , H01L29/08 , H01L29/66
CPC分类号： H01L29/785 , H01L21/02532 , H01L21/02554 , H01L21/02603 , H01L29/0669 , H01L29/0847 , H01L29/66795
摘要： Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

5. 发明公开

US20240170323A1 LOW THERMAL BUDGET DIELECTRIC FOR SEMICONDUCTOR DEVICES 审中-公开
公开(公告)号：US20240170323A1
公开(公告)日：2024-05-23
申请号：US18427575
申请日：2024-01-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Mrunal Abhijith KHADERBAD , Ko-Feng Chen , Zheng-Yong Liang , Chen-Han Wang , De-Yang Chiou , Yu-Yun Peng , Keng-Chu Lin
IPC分类号： H01L21/762 , H01L21/311 , H01L21/8234
CPC分类号： H01L21/76224 , H01L21/31116 , H01L21/823481
摘要： The present disclosure describes a method of forming low thermal budget dielectrics in semiconductor devices. The method includes forming, on a substrate, first and second fin structures with an opening in between, filling the opening with a flowable isolation material, treating the flowable isolation material with a plasma, and removing a portion of the plasma-treated flowable isolation material between the first and second fin structures

6. 发明授权

US11637062B2 Interconnect structure and method for manufacturing the interconnect structure 有权
公开(公告)号：US11637062B2
公开(公告)日：2023-04-25
申请号：US17676719
申请日：2022-02-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
发明人： Khaderbad Mrunal Abhijith , Yu-Yun Peng , Fu-Ting Yen , Chen-Han Wang , Tsu-Hsiu Perng , Keng-Chu Lin
IPC分类号： H01L23/522 , H01L23/532 , H01L21/768
摘要： The present disclosure provides an interconnect structure and a method for forming an interconnect structure. The method for forming an interconnect structure includes forming a first interlayer dielectric (ILD) layer over a substrate, forming a contact in the first ILD layer, forming a second ILD layer over the first ILD layer, forming a first opening in the second ILD layer and obtaining an exposed side surface of the second ILD layer over the contact, forming a densified dielectric layer at the exposed side surface of the second ILD layer, including oxidizing the exposed side surface of the second ILD layer by irradiating a microwave on the second ILD layer, and forming a via in contact with the densified dielectric layer.

7. 发明申请

US20150200271A1 Epitaxial Source/Drain Regions in FinFETs and Methods for Forming the Same 有权
标题翻译： FinFET中的外延源/漏区及其形成方法
公开(公告)号：US20150200271A1
公开(公告)日：2015-07-16
申请号：US14156230
申请日：2014-01-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tung Ying Lee , Chen-Han Wang
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7854
摘要： An embodiment is a structure including a substrate having a fin and an isolation region adjoining the fin, and a raised epitaxial source/drain region on the fin. A first lateral distance is between opposing exterior surfaces of the raised epitaxial source/drain region at an upper portion of the raised epitaxial source/drain region. A second lateral distance is between opposing exterior surfaces of the raised epitaxial source/drain region at a mid portion of the raised epitaxial source/drain region. A third lateral distance is between opposing exterior surfaces of the raised epitaxial source/drain region at a lower portion of the raised epitaxial source/drain region. The first lateral distance is greater than the second lateral distance, and the second lateral distance is less than the third lateral distance.
摘要翻译：一个实施例是一种结构，其包括具有翅片和邻接鳍片的隔离区域的衬底，以及翅片上升高的外延源极/漏极区域。第一横向距离在凸出的外延源极/漏极区的上部的凸起的外延源/漏极区的相对的外表面之间。在升高的外延源极/漏极区域的中部处，凸起的外延源极/漏极区域的相对的外部表面之间的第二横向距离。第三横向距离在凸起的外延源/漏区的下部处的凸起的外延源极/漏极区的相对的外表面之间。第一横向距离大于第二横向距离，并且第二横向距离小于第三横向距离。

8. 发明授权

US09496398B2 Epitaxial source/drain regions in FinFETs and methods for forming the same 有权
标题翻译： FinFET中的外延源极/漏极区及其形成方法
公开(公告)号：US09496398B2
公开(公告)日：2016-11-15
申请号：US14156230
申请日：2014-01-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tung Ying Lee , Chen-Han Wang
IPC分类号： H01L21/8234 , H01L21/336 , H01L29/78 , H01L29/66
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/7854
摘要： An embodiment is a structure including a substrate having a fin and an isolation region adjoining the fin, and a raised epitaxial source/drain region on the fin. A first lateral distance is between opposing exterior surfaces of the raised epitaxial source/drain region at an upper portion of the raised epitaxial source/drain region. A second lateral distance is between opposing exterior surfaces of the raised epitaxial source/drain region at a mid portion of the raised epitaxial source/drain region. A third lateral distance is between opposing exterior surfaces of the raised epitaxial source/drain region at a lower portion of the raised epitaxial source/drain region. The first lateral distance is greater than the second lateral distance, and the second lateral distance is less than the third lateral distance.
摘要翻译：一个实施例是一种结构，其包括具有翅片和邻接鳍片的隔离区域的衬底，以及翅片上升高的外延源极/漏极区域。第一横向距离在凸出的外延源极/漏极区的上部的凸起的外延源/漏极区的相对的外表面之间。在升高的外延源极/漏极区域的中部处，凸起的外延源极/漏极区域的相对的外部表面之间的第二横向距离。第三横向距离在凸起的外延源/漏区的下部处的凸起的外延源极/漏极区的相对的外表面之间。第一横向距离大于第二横向距离，并且第二横向距离小于第三横向距离。

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