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1. 发明授权

US11730058B2 Integrated heater (and related method) to recover degraded piezoelectric device performance 有权
公开(公告)号：US11730058B2
公开(公告)日：2023-08-15
申请号：US16413839
申请日：2019-05-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Alexander Kalnitsky , Chun-Ren Cheng , Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yan-Jie Liao
IPC分类号： H01L41/193 , H01L41/08 , H01L41/113 , D01F6/62 , H10N30/00 , H10N30/04 , H10N30/067 , H10N30/87 , H10N30/063
CPC分类号： H10N30/10513 , H10N30/04 , H10N30/067 , H10N30/877 , H10N30/063
摘要： In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

2. 发明授权

US11289568B2 Reduction of electric field enhanced moisture penetration by metal shielding 有权
公开(公告)号：US11289568B2
公开(公告)日：2022-03-29
申请号：US16410259
申请日：2019-05-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Wen-Chuan Tai , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Anderson Lin , Fu-Chun Huang , Chun-Ren Cheng , Ivan Hua-Shu Wu , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC分类号： H01L49/02 , H01L23/58 , H01L23/00
摘要： The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

3. 发明授权

US09493346B2 Capacitor with planarized bonding for CMOS-MEMS integration 有权
标题翻译：具有用于CMOS-MEMS集成的平面结合的电容器
公开(公告)号：US09493346B2
公开(公告)日：2016-11-15
申请号：US14445226
申请日：2014-07-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wei-Cheng Shen , Yi-Hsien Chang , Yi Heng Tsai , Tzu-Heng Wu , Chun-Ren Cheng , Chun-Wen Cheng
IPC分类号： B81C1/00 , B81B7/00
CPC分类号： B81C1/00238
摘要： An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.
摘要翻译：提供集成电路（IC）结构。 IC结构包括IC基板，其包括通过布置在其上的导电互连结构耦合在一起的有源器件。导电互连结构包括布置在相邻的水平导电层之间的一系列水平导电层和电介质区域。导电互连结构包括具有平坦顶表面区域的最上面的导电水平区域。 MEMS基板布置在IC基板上方，并且包括柔性或可移动的结构，其以施加到柔性或可移动结构的力相应地弯曲或移动。 IC基板的有源器件被布置成建立分析电路，以便于电测量最上面的导电水平区域和柔性或可移动结构之间的电容。

4. 发明授权

US09449867B2 VHF etch barrier for semiconductor integrated microsystem 有权
标题翻译：用于半导体集成微系统的VHF蚀刻屏障
公开(公告)号：US09449867B2
公开(公告)日：2016-09-20
申请号：US14306643
申请日：2014-06-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tzu-Heng Wu , Yi-Hsien Chang , Kai-Chih Liang , Yi Heng Tsai , Wei-Cheng Shen , Chun-Ren Cheng , Chun-Wen Cheng , Han-Chin Chiu
IPC分类号： B81C3/00 , B81B7/00 , H01L21/762 , H01L23/00 , H01L27/092
CPC分类号： H01L21/76232 , B81B7/0025 , B81B7/0054 , B81B7/008 , B81C1/00238 , B81C1/00801 , B81C3/001 , H01L24/89 , H01L27/092
摘要： The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.
摘要翻译：本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF）死。第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。

5. 发明申请

US20150364363A1 VHF ETCH BARRIER FOR SEMICONDUCTOR INTEGRATED MICROSYSTEM 有权
标题翻译：用于SEMICONDUCTOR INTEGRATED MICROSYSTEM的VHF ETCH BARRIER
公开(公告)号：US20150364363A1
公开(公告)日：2015-12-17
申请号：US14306643
申请日：2014-06-17
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tzu-Heng Wu , Yi-Hsien Chang , Kai-Chih Liang , Yi Heng Tsai , Wei-Cheng Shen , Chun-Ren Cheng , Chun-Wen Cheng , Han-Chin Chiu
IPC分类号： H01L21/762 , B81C3/00 , B81B7/00 , H01L27/092 , H01L23/00
CPC分类号： H01L21/76232 , B81B7/0025 , B81B7/0054 , B81B7/008 , B81C1/00238 , B81C1/00801 , B81C3/001 , H01L24/89 , H01L27/092
摘要： The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.
摘要翻译：本公开涉及具有保护屏障结构的集成微系统以及相关联的方法。在一些实施例中，集成微系统包括具有设置在其上的多个CMOS器件的第一管芯，具有设置在其上的多个MEMS器件的第二管芯和设置在第一管芯和第二管芯之间的蒸气氢氟酸（vHF）死。第二管芯在接合界面区域与第一管芯接合。 vHF蚀刻阻挡结构包括位于第一管芯的上表面上方的vHF阻挡层，以及布置在第一管芯的上表面之间的应力减小层。

6. 发明授权

US11107630B2 Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device 有权
公开(公告)号：US11107630B2
公开(公告)日：2021-08-31
申请号：US16417797
申请日：2019-05-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Anderson Lin , Chun-Ren Cheng , Chi-Yuan Shih , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Fu-Chun Huang , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC分类号： H01G4/012 , H01G4/228 , H01L49/02 , H01L21/3213 , H01L21/311 , H01G4/12 , H01L41/113 , H01L41/083 , H01L41/047
摘要： Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.

7. 发明申请

US20160031704A1 CAPACITOR WITH PLANARIZED BONDING FOR CMOS-MEMS INTEGRATION 有权
标题翻译：具有用于CMOS-MEMS集成的平面结合的电容器
公开(公告)号：US20160031704A1
公开(公告)日：2016-02-04
申请号：US14445226
申请日：2014-07-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wei-Cheng Shen , Yi-Hsien Chang , Yi Heng Tsai , Tzu-Heng Wu , Chun-Ren Cheng , Chun-Wen Cheng
IPC分类号： B81B7/00 , B81C1/00
CPC分类号： B81C1/00238
摘要： An integrated circuit (IC) structure is provided. The IC structure includes an IC substrate including active devices which are coupled together through a conductive interconnect structure arranged thereover. The conductive interconnect structure includes a series of horizontal conductive layers and dielectric regions arranged between neighboring horizontal conductive layers. The conductive interconnect structure includes an uppermost conductive horizontal region with a planar top surface region. A MEMS substrate is arranged over the IC substrate and includes a flexible or moveable structure that flexes or moves commensurate with a force applied to the flexible or moveable structure. The active devices of the IC substrate are arranged to establish analysis circuitry to facilitate electrical measurement of a capacitance between the uppermost conductive horizontal region and the flexible or moveable structure.
摘要翻译：提供集成电路（IC）结构。 IC结构包括IC基板，其包括通过布置在其上的导电互连结构耦合在一起的有源器件。导电互连结构包括布置在相邻的水平导电层之间的一系列水平导电层和电介质区域。导电互连结构包括具有平坦顶表面区域的最上面的导电水平区域。 MEMS基板布置在IC基板上方，并且包括柔性或可移动的结构，其以施加到柔性或可移动结构的力相应地弯曲或移动。 IC基板的有源器件被布置成建立分析电路，以便于电测量最上面的导电水平区域和柔性或可移动结构之间的电容。

8. 发明申请

US20200098969A1 INTEGRATED HEATER (AND RELATED METHOD) TO RECOVER DEGRADED PIEZOELECTRIC DEVICE PERFORMANCE 审中-公开
公开(公告)号：US20200098969A1
公开(公告)日：2020-03-26
申请号：US16413839
申请日：2019-05-16
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Alexander Kalnitsky , Chun-Ren Cheng , Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yan-Jie Liao
IPC分类号： H01L41/08 , H01L41/047 , H01L41/297
摘要： In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

9. 发明申请

US20200098517A1 NOVEL INTEGRATION SCHEME FOR BREAKDOWN VOLTAGE ENHANCEMENT OF A PIEZOELECTRIC METAL-INSULATOR-METAL DEVICE 审中-公开
公开(公告)号：US20200098517A1
公开(公告)日：2020-03-26
申请号：US16417797
申请日：2019-05-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Anderson Lin , Chun-Ren Cheng , Chi-Yuan Shih , Shih-Fen Huang , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Fu-Chun Huang , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC分类号： H01G4/012 , H01G4/228 , H01L49/02 , H01L21/3213 , H01L21/311 , H01G4/12
摘要： Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.

10. 发明申请

US20200006469A1 REDUCTION OF ELECTRIC FIELD ENHANCED MOISTURE PENETRATION BY METAL SHIELDING 审中-公开
公开(公告)号：US20200006469A1
公开(公告)日：2020-01-02
申请号：US16410259
申请日：2019-05-13
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chi-Yuan Shih , Kai-Fung Chang , Shih-Fen Huang , Wen-Chuan Tai , Yi-Chuan Teng , Yi Heng Tsai , You-Ru Lin , Yen-Wen Chen , Anderson Lin , Fu-Chun Huang , Chun-Ren Cheng , Ivan Hua-Shu Wu , Fan Hu , Ching-Hui Lin , Yan-Jie Liao
IPC分类号： H01L49/02 , H01L23/58
摘要： The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.

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