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1. 发明申请

US20150063040A1 THREE DIMENSIONAL CROSS-ACCESS DUAL-PORT BIT CELL DESIGN 有权
标题翻译：三维交叉双端口单元设计
公开(公告)号：US20150063040A1
公开(公告)日：2015-03-05
申请号：US14014431
申请日：2013-08-30
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wei Min CHAN , Kao-Cheng LIN , Yen-Huei CHEN
IPC分类号： G11C11/419
CPC分类号： G11C8/16 , G11C5/06 , G11C5/063 , G11C8/08 , G11C8/14 , G11C11/41 , G11C11/412 , G11C11/413 , G11C11/417
摘要： A semiconductor memory comprises a dual-port memory array having a plurality of cross-access dual-port bit cells arranged in a plurality of rows and a plurality of columns, wherein each of the plurality of cross-access dual-port bit cells has two cross-access ports for read and write of one or more bits of data to the cross-access dual port bit cell. The semiconductor memory further comprises a pair of word lines associated with at least one of the plurality of rows of the dual-port memory array, wherein the pair of word lines is configured to carry a pair of row selection signals for enabling one or more read and write operations on one or more cross-access dual-port bit cells in the row. The semiconductor memory further comprises a pair of column selection lines associated with at least one of the plurality of columns of the dual port memory array, wherein the pair of column selection lines is configured to carry a pair of column selection signals for enabling the cross-access dual-port bit cells in the column during the read and write operations.
摘要翻译：半导体存储器包括双端口存储器阵列，其具有以多行和多列布置的多个交叉访问双端口位单元，其中多个交叉访问双端口位单元中的每一个具有两个交叉访问端口用于读取和写入一个或多个位数据到交叉访问双端口位单元。半导体存储器还包括与双端口存储器阵列的多行中的至少一个相关联的一对字线，其中该对字线被配置为携带一对行选择信号，以使一个或多个读取并对行中的一个或多个交叉访问双端口位单元进行写入操作。半导体存储器还包括与双端口存储器阵列的多个列中的至少一个相关联的一对列选择线，其中该列选择线被配置为承载一对列选择信号，在读取和写入操作期间访问列中的双端口位单元。

2. 发明申请

US20200081636A1 CONFIGURABLE MEMORY STORAGE SYSTEM 审中-公开
公开(公告)号：US20200081636A1
公开(公告)日：2020-03-12
申请号：US16685722
申请日：2019-11-15
申请人： Taiwan Semiconductor Manufacturing Co. Ltd.
发明人： Yu-Hao HSU , Cheng Hung LEE , Chen-Lin YANG , Chiting CHENG , Fu-An WU , Hung-Jen LIAO , Jung-Ping YANG , Jonathan Tsung-Yung CHANG , Wei Min CHAN , Yen-Huei CHEN , Yangsyu LIN , Chien-Chen LIN
IPC分类号： G06F3/06 , H04J14/02 , H04B10/27 , H04B10/03 , G11C16/12 , G11C5/14 , G11C16/30 , G11C11/4074
摘要： Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

3. 发明申请

US20170148507A1 THREE DIMENSIONAL DUAL-PORT BIT CELL AND METHOD OF USING SAME 审中-公开
公开(公告)号：US20170148507A1
公开(公告)日：2017-05-25
申请号：US15422529
申请日：2017-02-02
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Wei Min CHAN , Wei-Cheng WU , Yen-Huei CHEN
IPC分类号： G11C11/419 , H01L27/06 , H01L27/11
CPC分类号： G11C11/419 , G11C5/025 , G11C8/08 , G11C8/16 , G11C11/412 , G11C11/413 , H01L27/0688 , H01L27/1104 , H01L2224/48227 , H01L2224/73265
摘要： A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

4. 发明申请

US20220236894A1 CONFIGURABLE MEMORY STORAGE SYSTEM 有权
公开(公告)号：US20220236894A1
公开(公告)日：2022-07-28
申请号：US17717491
申请日：2022-04-11
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Hao HSU , Cheng Hung LEE , Chen-Lin YANG , Chiting CHENG , Fu-An WU , Hung-Jen LIAO , Jung-Ping YANG , Jonathan Tsung-Yung CHANG , Wei Min CHAN , Yen-Huei CHEN , Yangsyu LIN , Chien-Chen LIN
IPC分类号： G06F3/06 , G11C5/14 , G11C11/4074 , G11C16/12 , G11C16/30 , H04B10/03 , H04B10/27 , H04J14/02
摘要： Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum voltage signal from among the multiple voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum voltage signal from among the multiple voltage signals to minimize power consumption.

5. 发明申请

US20150092476A1 DUAL PORT SRAM WITH DUMMY READ RECOVERY 有权
标题翻译：双端口SRAM与DUMMY READ RECOVERY
公开(公告)号：US20150092476A1
公开(公告)日：2015-04-02
申请号：US14043869
申请日：2013-10-02
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Kao-Cheng LIN , Wei Min CHAN , Yen-Huei CHEN
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C7/1075 , G11C8/16 , G11C11/412
摘要： An integrated includes a dual port memory cell such as a SRAM cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line. A second port dummy read recovery block couples the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the first port bit line, and couples the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the first port complementary bit line.
摘要翻译：集成的包括诸如SRAM单元的双端口存储单元。第一端口虚拟读取恢复块在写入逻辑低操作期间通过第二端口位线将第一端口互补位线耦合到高电压供应节点到数据节点，并且将第一端口位线耦合到高电压供应节点在通过第二端口互补位线到互补数据节点的写入逻辑低操作期间。第二端口虚拟读恢复块在写逻辑低操作期间通过第一端口位线将第二端口互补位线耦合到高电压电源节点，并将第二端口位线耦合到高电压电源节点在通过第一端口互补位线到互补数据节点的写入逻辑低操作期间。

6. 发明申请

US20140210100A1 CONDUCTIVE LINE ROUTING FOR MULTI-PATTERNING TECHNOLOGY 有权
标题翻译：导线技术的导线路由
公开(公告)号：US20140210100A1
公开(公告)日：2014-07-31
申请号：US13755326
申请日：2013-01-31
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： You-Cheng XIAO , Wei Min CHAN , Ken-Hsien HSIEH
IPC分类号： H01L21/768 , G06F17/50 , H01L23/48
CPC分类号： H01L23/5226 , G06F17/5068 , G06F17/5077 , G06F2217/78 , H01L21/76838 , H01L23/481 , H01L23/528 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.
摘要翻译：一种方法包括：使用第一掩模在半导体衬底的第一层中形成多个参考电压图案，所述参考电压图案包括交替的第一参考电压图案和第二参考电压图案; 以及使用第二掩模在所述半导体衬底的第一层中形成多个信号图案，所述多个信号图案中的一个信号图案位于连续的参考电压图案对之间。

7. 发明申请

US20160027501A1 THREE DIMENSIONAL DUAL-PORT BIT CELL AND METHOD OF USING SAME 审中-公开
公开(公告)号：US20160027501A1
公开(公告)日：2016-01-28
申请号：US14874626
申请日：2015-10-05
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Wei Min CHAN , Wei-Cheng WU , Yen-Huei CHEN
IPC分类号： G11C11/419
CPC分类号： G11C11/419 , G11C5/025 , G11C8/08 , G11C8/16 , G11C11/412 , G11C11/413 , H01L27/0688 , H01L27/1104 , H01L2224/48227 , H01L2224/73265
摘要： A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

8. 发明申请

US20210200452A1 CONFIGURABLE MEMORY STORAGE SYSTEM 有权
公开(公告)号：US20210200452A1
公开(公告)日：2021-07-01
申请号：US17201931
申请日：2021-03-15
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Yu-Hao HSU , Cheng Hung LEE , Chen-Lin YANG , Chiting CHENG , Fu-An WU , Hung-Jen LIAO , Jung-Ping YANG , Jonathan Tsung-Yung CHANG , Wei Min CHAN , Yen-Huei CHEN , Yangsyu LIN , Chien-Chen LIN
IPC分类号： G06F3/06 , G11C11/4074 , G11C16/30 , G11C5/14 , G11C16/12 , H04B10/03 , H04B10/27 , H04J14/02
摘要： Various embodiments for configurable memory storage systems are disclosed. The configurable memory storages selectively choose an operational voltage signal from among multiple operational voltage signals to dynamically control various operational parameters. For example, the configurable memory storages selectively choose a maximum operational voltage signal from among the multiple operational voltage signals to maximize read/write speed. As another example, the configurable memory storages selectively choose a minimum operational voltage signal from among the multiple operational voltage signals to minimize power consumption.

9. 发明申请

US20150243600A1 CONDUCTIVE LINE ROUTING FOR MULTI-PATTERNING TECHNOLOGY 审中-公开
标题翻译：导线技术的导线路由
公开(公告)号：US20150243600A1
公开(公告)日：2015-08-27
申请号：US14708333
申请日：2015-05-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： You-Cheng XIAO , Wei Min CHAN , Ken-Hsien HSIEH
IPC分类号： H01L23/522 , H01L23/528 , H01L27/11 , G06F17/50
CPC分类号： H01L23/5226 , G06F17/5068 , G06F17/5077 , G06F2217/78 , H01L21/76838 , H01L23/481 , H01L23/528 , H01L27/11 , H01L2924/0002 , H01L2924/00
摘要： A method comprises: forming a plurality of reference voltage patterns in a first layer of a semiconductor substrate using a first mask, the reference voltage patterns including alternating first reference voltage patterns and second reference voltage patterns; and forming a plurality of signal patterns in the first layer of the semiconductor substrate using a second mask, ones of the plurality of signal patterns located between successive pairs of reference voltage patterns.
摘要翻译：一种方法包括：使用第一掩模在半导体衬底的第一层中形成多个参考电压图案，所述参考电压图案包括交替的第一参考电压图案和第二参考电压图案; 以及使用第二掩模在所述半导体衬底的第一层中形成多个信号图案，所述多个信号图案中的一个信号图案位于连续的参考电压图案对之间。

10. 发明申请

US20150085556A1 THREE DIMENSIONAL DUAL-PORT BIT CELL AND METHOD OF USING SAME 有权
标题翻译：三维双端口单元及其使用方法
公开(公告)号：US20150085556A1
公开(公告)日：2015-03-26
申请号：US14032222
申请日：2013-09-20
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Wei Min CHAN , Wei-Cheng WU , Yen-Huei CHEN
IPC分类号： G11C5/06 , H01L27/11 , G11C11/412
CPC分类号： G11C11/419 , G11C5/025 , G11C8/08 , G11C8/16 , G11C11/412 , G11C11/413 , H01L27/0688 , H01L27/1104 , H01L2224/48227 , H01L2224/73265
摘要： A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
摘要翻译：三维双端口位单元通常包括设置在第一层上的第一部分，其中第一部分包括多个端口元件。双端口位单元还包括设置在使用至少一个通孔相对于第一层垂直堆叠的第二层上的第二部分，其中第二部分包括闩锁。

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