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1. 发明申请

US20220223474A1 Methods for Forming Self-Aligned Interconnect Structures 有权
公开(公告)号：US20220223474A1
公开(公告)日：2022-07-14
申请号：US17705487
申请日：2022-03-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ru-Gun Liu , Shih-Ming Chang , Hoi-Tou Ng
IPC分类号： H01L21/768 , H01L21/311 , H01L21/027 , H01L23/522
摘要： The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a first conductive feature embedded in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. The first conductive feature includes a metal layer and a reflective layer on the metal layer. The reflective layer has a reflectivity higher than the metal layer.

2. 发明授权

US11294286B2 Pattern formation method using a photo mask for manufacturing a semiconductor device 有权
公开(公告)号：US11294286B2
公开(公告)日：2022-04-05
申请号：US16287450
申请日：2019-02-27
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Ru-Gun Liu , Chin-Hsiang Lin , Cheng-I Huang , Chih-Ming Lai , Chien-Wen Lai , Ken-Hsien Hsieh , Shih-Ming Chang , Yuan-Te Hou
IPC分类号： G03F7/20 , G03F1/42 , G03F1/68 , G03F1/50
摘要： A photo mask for manufacturing a semiconductor device includes a first pattern extending in a first direction, a second pattern extending in the first direction and aligned with the first pattern, and a sub-resolution pattern extending in the first direction, disposed between an end of the first pattern and an end of the second pattern. A width of the first pattern and a width of the second pattern are equal to each other, and the first pattern and the second pattern are for separate circuit elements in the semiconductor device.

3. 发明授权

US11289376B2 Methods for forming self-aligned interconnect structures 有权
公开(公告)号：US11289376B2
公开(公告)日：2022-03-29
申请号：US16892984
申请日：2020-06-04
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ru-Gun Liu , Shih-Ming Chang , Hoi-Tou Ng
IPC分类号： H01L21/768 , H01L21/311 , H01L21/027 , H01L23/522
摘要： The present disclosure provides a method for forming interconnect structures. The method includes providing a semiconductor structure including a substrate and a conductive feature formed in a top portion of the substrate; depositing a resist layer over the substrate, wherein the resist layer has an exposure threshold; providing a radiation with an incident exposure dose to the resist layer, wherein the incident exposure dose is configured to be less than the exposure threshold of the resist layer while a sum of the incident exposure dose and a reflected exposure dose from a top surface of the conductive feature is larger than the exposure threshold of the resist layer, thereby forming a latent pattern above the conductive feature; and developing the resist layer to form a patterned resist layer.

4. 发明授权

US11054748B2 Dummy insertion for improving throughput of electron beam lithography 有权
公开(公告)号：US11054748B2
公开(公告)日：2021-07-06
申请号：US16138402
申请日：2018-09-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
IPC分类号： G03F7/20 , G03F1/36 , G03F1/78
摘要： An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

5. 发明授权

US10698320B2 Method for optimized wafer process simulation 有权
公开(公告)号：US10698320B2
公开(公告)日：2020-06-30
申请号：US15427496
申请日：2017-02-08
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ru-Gun Liu , Shih-Ming Chang , Shuo-Yen Chou , Zengqin Zhao , Chien Wen Lai
IPC分类号： G03F7/20 , G03F9/00 , H01L23/544
摘要： A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.

6. 发明申请

US20200098545A1 Dummy Insertion for Improving Throughput of Electron Beam Lithography 审中-公开
公开(公告)号：US20200098545A1
公开(公告)日：2020-03-26
申请号：US16138402
申请日：2018-09-21
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Ming Chang , Wen Lo , Chun-Hung Liu , Chia-Hua Chang , Hsin-Wei Wu , Ta-Wei Ou , Chien-Chih Chen , Chien-Cheng Chen
IPC分类号： H01J37/317 , H01J37/302 , G03F7/20 , G03F1/78
摘要： An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

7. 发明授权

US10514613B2 Pattern modification and patterning process 有权
公开(公告)号：US10514613B2
公开(公告)日：2019-12-24
申请号：US15398839
申请日：2017-01-05
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Ming Chang , Ru-Gun Liu , Shuo-Yen Chou , Chien-Wen Lai , Zengqin Zhao
IPC分类号： G03B27/52 , G03F7/20 , G03F7/038 , G03F7/039 , G03F7/34
摘要： A pattern modification method and a patterning process are provided. The method includes extracting a first pattern and a second pattern to be respectively transferred to a first target portion and a second target portion of a resist layer. The method also includes obtaining regional information of the first target portion and the second target portion. The method includes determining a first desired focus position for transferring the first pattern based on the regional information. In addition, the method includes determining a second desired focus position for transferring the second pattern based on the regional information. The method includes modifying one or both of the first pattern and the second pattern. As a result, focus positions of the first pattern and the second pattern are shifted to be substantially and respectively positioned at the first desired focus position and the second desired focus position during an exposure operation.

8. 发明申请

US20180165388A1 Method for Optimized Wafer Process Simulation 审中-公开
公开(公告)号：US20180165388A1
公开(公告)日：2018-06-14
申请号：US15427496
申请日：2017-02-08
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ru-Gun Liu , Shih-Ming Chang , Shuo-Yen Chou , Zengqin Zhao , Chien Wen Lai
IPC分类号： G06F17/50
摘要： A method includes establishing a simulation process for simulating fabrication of a structure on a wafer. The simulation process includes multiple simulation steps for simulating multiple wafer fabrication steps respectively, and further includes a step of testing the structure that produces a result representing quality of the structure. Each of the simulation steps has a respective adjustable process parameter. The method further includes specifying a respective workable range for each process parameter and running the simulation process in iterations using a wafer process simulator until the result becomes optimal. During the running of the simulation process, every two consecutive iterations either adjust two different process parameters within their workable ranges or adjust a same process parameter at opposite directions within its workable range.

9. 发明授权

US09541846B2 Homogeneous thermal equalization with active device 有权
标题翻译：有源器件的均匀热均衡
公开(公告)号：US09541846B2
公开(公告)日：2017-01-10
申请号：US14019614
申请日：2013-09-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Ming Chang
IPC分类号： G03B27/32 , G03B27/52 , G03B27/58 , H02K41/02 , G03F7/20
CPC分类号： G03F7/70875 , G03F7/70866
摘要： A system and method is provided for providing a thermal distribution on a workpiece during a lithographic process. The system provides a source of lithographic energy to workpiece, such as a workpiece having a lithographic film formed thereover. A workpiece support having a plurality of thermal devices embedded therein is configured to support the workpiece concurrent to an exposure of the workpiece to the lithographic energy. A controller individually controls a temperature of each of the plurality of thermal devices, therein controlling a specified temperature distribution across the workpiece associated with the exposure of the workpiece to the lithographic energy. Controlling the temperature of the thermal devices can be based on a model, a measured temperature of the workpiece, and/or a prediction of a temperature at one or more locations on the workpiece.
摘要翻译：提供了一种用于在光刻工艺期间在工件上提供热分布的系统和方法。该系统为工件提供光刻能源，例如在其上形成有平版印刷膜的工件。具有嵌入其中的多个热装置的工件支撑件构造成与工件暴露于平版印刷能量同时支撑工件。控制器单独地控制多个热装置中的每一个的温度，其中控制与工件的曝光相关联的与工件的光刻能量相关的工件的规定温度分布。控制热装置的温度可以基于模型，工件的测量温度和/或工件上一个或多个位置处的温度预测。

10. 发明授权

US11556058B2 Proximity effect correction in electron beam lithography 有权
公开(公告)号：US11556058B2
公开(公告)日：2023-01-17
申请号：US16664425
申请日：2019-10-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Wen Lo , Shih-Ming Chang
IPC分类号： H01J37/317 , H01J37/304 , G03F7/20
摘要： A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.

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