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1. 发明授权

US07710835B2 High resolution time detecting apparatus using interpolation and time detecting method using the same 有权
标题翻译：高分辨率时间检测装置，使用内插法和时间检测方法
公开(公告)号：US07710835B2
公开(公告)日：2010-05-04
申请号：US11935424
申请日：2007-11-06
申请人： Tae-wook Kim , Choong-yul Cha , Jae-sup Lee , Kang-yoon Lee
发明人： Tae-wook Kim , Choong-yul Cha , Jae-sup Lee , Kang-yoon Lee
IPC分类号： G04F8/00 , G04F10/00
CPC分类号： H03D13/00 , H03L7/091 , H03L2207/50
摘要： A high resolution time detecting apparatus using interpolation and a time detecting method using the same are provided. The time detecting apparatus includes a delayer which generates delayed signals by sequentially delaying a reference signal using a plurality of delay elements, a latch unit which outputs latch signals using the delayed signals, and an interpolation unit which outputs interpolated signals using input and output signals of the delay elements. As a result, a high resolution TDC using an interpolation and a time detecting method using the same provide improved performance of digital PLL, high resolution digital signal output at a low power consumption, and controlled circuit size.
摘要翻译：提供了使用内插的高分辨率时间检测装置和使用其的时间检测方法。时间检测装置包括：延迟器，其通过使用多个延迟元件顺序延迟参考信号来产生延迟信号;锁存单元，其使用延迟信号输出锁存信号;以及内插单元，其使用输入和输出信号输出内插信号延迟元素。结果，使用内插的高分辨率TDC和使用其的时间检测方法提供了数字PLL，低功耗的高分辨率数字信号输出和受控电路尺寸的改进的性能。

2. 发明授权

US07915968B2 Digitally controlled oscillator (DCO) 有权
标题翻译：数字控制振荡器（DCO）
公开(公告)号：US07915968B2
公开(公告)日：2011-03-29
申请号：US12104494
申请日：2008-04-17
申请人： Tae-wook Kim , Choong-yul Cha , Jae-sup Lee , Kang-yoon Lee
发明人： Tae-wook Kim , Choong-yul Cha , Jae-sup Lee , Kang-yoon Lee
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1253 , H03B5/1259 , H03B5/1271 , H03B5/1293
摘要： A digitally controlled oscillator (DCO) includes a current generator which generates an electric current having a magnitude corresponding to an input signal, and a digitally controlled oscillating unit which generates an oscillating frequency based on an inductance which varies according to the magnitude of the electric current generated by the current generator.
摘要翻译：数字控制振荡器（DCO）包括产生具有对应于输入信号的幅度的电流的电流发生器，以及数字控制的振荡单元，其基于根据电流的大小而变化的电感产生振荡频率由当前发电机产生。

3. 发明申请

US20110186923A1 SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20110186923A1
公开(公告)日：2011-08-04
申请号：US13085898
申请日：2011-04-13
申请人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
发明人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
IPC分类号： H01L29/78
CPC分类号： H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated
摘要翻译：两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件。像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，使得容易制造高度集成的半导体存储器件

4. 发明申请

US20080179647A1 SEMICONDUCTOR DEVICE COMPRISING A BARRIER INSULATING LAYER AND RELATED METHOD 审中-公开
标题翻译：包含障壁绝缘层的半导体器件及相关方法
公开(公告)号：US20080179647A1
公开(公告)日：2008-07-31
申请号：US11964146
申请日：2007-12-26
申请人： Hyeoung-won Seo , Dong-hyun Kim , Kang-yoon Lee , Seong-goo Kim
发明人： Hyeoung-won Seo , Dong-hyun Kim , Kang-yoon Lee , Seong-goo Kim
IPC分类号： H01L27/108 , H01L21/8239
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10823 , H01L27/10876
摘要： A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.
摘要翻译：公开了一种包括阻挡绝缘层和相关制造方法的半导体器件。半导体器件半导体衬底包括多个有源区，其中有源区由器件隔离层限定，并沿着第一方向设置; 连接到有源区的多个位线电极，其中每个位线电极沿着第二方向延伸; 以及多个第一阻挡绝缘层。每个第一阻挡绝缘层沿着第三方向延伸，至少一个第一阻挡绝缘层设置在设置在两个有源区之间的器件隔离层的对应的第一部分上，两个有源区相邻沿第一方向，第一方向和第二方向彼此不同。

5. 发明授权

US07387931B2 Semiconductor memory device with vertical channel transistor and method of fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US07387931B2
公开(公告)日：2008-06-17
申请号：US11546581
申请日：2006-10-11
申请人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
发明人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L29/66666 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/7827
摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.
摘要翻译：在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。形成围绕每个支柱部分的栅电极。位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。第一掺杂区域形成在柱的每个柱部分的上表面中。第二掺杂区形成在柱的主体部分上并与电位线连接。存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

6. 发明授权

US5900659A Buried bit line DRAM cells 失效
标题翻译：埋地位线DRAM单元
公开(公告)号：US5900659A
公开(公告)日：1999-05-04
申请号：US987281
申请日：1997-12-09
申请人： Kang-yoon Lee
发明人： Kang-yoon Lee
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/74 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/743 , H01L27/10808 , Y10S257/908
摘要： A buried bit line DRAM cell includes an active region having a protruding tap, formed in a semiconductor substrate. A device isolation region is formed in the substrate, outside the active region. A bit line laterally contacts the tap and is buried in the device isolation region. Accordingly, photolithography steps for forming a device isolation film twice and for forming a bit line contact can be omitted, thereby obtaining process simplicity and wider process margins.
摘要翻译：掩埋位线DRAM单元包括形成在半导体衬底中的具有突出抽头的有源区。器件隔离区形成在衬底中，在有源区之外。位线横向接触抽头并被埋在设备隔离区域中。因此，可以省略用于形成器件隔离膜两次并形成位线接触的光刻步骤，从而获得工艺简单性和更宽的工艺裕度。

7. 发明授权

US08283714B2 Semiconductor memory device having vertical channel transistor and method for fabricating the same 有权
标题翻译：具有垂直沟道晶体管的半导体存储器件及其制造方法
公开(公告)号：US08283714B2
公开(公告)日：2012-10-09
申请号：US13085898
申请日：2011-04-13
申请人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
发明人： Hyeoung-won Seo , Bong-soo Kim , Dong-gun Park , Kang-yoon Lee , Jae-man Yoon , Seong-goo Kim , Seung-bae Park
IPC分类号： H01L29/94
CPC分类号： H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10888 , H01L27/10891
摘要： Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
摘要翻译：两个晶体管的沟道垂直地形成在一个有源区的两个相对的侧表面的部分上，并且栅极垂直地形成在与有源区的沟道接触的器件隔离层上。在有源区域的中心部分形成共同的位线接触插塞，在位线接触插塞的两侧形成两个存储节点接触插塞，并且在位线接触插头的侧面上形成绝缘间隔件。像现有的半导体存储器件一样，在半导体衬底上顺序层叠字线，位线和电容器。因此，存储单元的有效空间布置是可能的，使得构成4F2结构，并且可以应用常规的线和接触形成工艺，从而容易地制造高度集成的半导体存储器件。

8. 发明申请

US20080211013A1 SEMICONDUCTOR MEMORY DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体存储器件及其制造方法
公开(公告)号：US20080211013A1
公开(公告)日：2008-09-04
申请号：US12118268
申请日：2008-05-09
申请人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
发明人： Hyeoung-won Seo , Jae-man Yoon , Kang-yoon Lee , Dong-gun Park , Bong-soo Kim , Seong-goo Kim
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L27/0207 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/7827
摘要： In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.
摘要翻译：在具有其主体连接到基板的垂直沟道晶体管的半导体存储器件及其制造方法中，半导体存储器件包括：半导体衬底，其包括彼此间隔布置的多个柱，并且每个支柱包括主体部分和从主体部分延伸并彼此间隔开的一对柱部分。形成围绕每个支柱部分的栅电极。位于所述主体部分上的位线穿过所述第一支柱中的所述第一支柱的一对支柱之间的区域，所述第一支柱布置成沿第一方向延伸。字线布置在位线之外，布置成沿与第一方向相交的第二方向延伸，并且被配置为接触栅电极的侧表面。第一掺杂区域形成在柱的每个柱部分的上表面中。第二掺杂区形成在柱的主体部分上并与电位线连接。存储节点电极与第一掺杂区域电连接并设置在每个柱部分上。

9. 发明授权

US5795801A MethodS of fabricating profiled device wells for improved device isolation 失效
标题翻译：制造异型设备井的方法，以改进设备隔离
公开(公告)号：US5795801A
公开(公告)日：1998-08-18
申请号：US694641
申请日：1996-08-09
申请人： Kang-yoon Lee
发明人： Kang-yoon Lee
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/336 , H01L21/76 , H01L21/762 , H01L21/763 , H01L29/78 , H01L21/8238
CPC分类号： H01L21/763 , H01L21/76232 , H01L21/76237 , Y10S148/085 , Y10S148/086
摘要： A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate. Preferably, the first doping includes implanting ions into the substrate through the trench insulation region and the trench sidewall using the barrier region as a mask. The second doping preferably is preceded by removal of the barrier region, and includes implanting ions into the substrate through the active region surface. The first implantation preferably occurs at a predetermined angle of incidence oblique to the active region surface or, more preferably, over a predetermined range of angles of incidence. The first and second doping steps may include doping with impurities of the same conductivity type or with opposite conductivity types.
摘要翻译：在衬底中形成沟槽，沟槽在衬底上限定有源区表面，沟槽具有沟槽侧壁。然后在沟槽中形成沟槽绝缘区域。在沟槽侧壁下面的衬底掺杂有杂质，并且在第一掺杂之后，有源区表面下面的衬底掺杂杂质以形成具有以预定方式朝向沟槽侧壁增加的杂质浓度的阱。为了形成沟槽，优选在衬底上形成绝缘层，在绝缘层上形成阻挡层，并对阻挡层和绝缘层进行图案化以在衬底上形成绝缘区域，并且在绝缘体上形成阻挡区域地区。然后使用阻挡区域和绝缘区域作为掩模蚀刻衬底，从而在衬底中形成沟槽。优选地，第一掺杂包括通过沟槽绝缘区域和使用屏障区域作为掩模的沟槽侧壁将离子注入到衬底中。优选在第二掺杂之前除去阻挡区，并且包括通过有源区表面将离子注入到衬底中。第一植入优选地以与活性区域表面倾斜的预定入射角发生，或者更优选地在预定的入射角范围内发生。第一和第二掺杂步骤可以包括掺杂相同导电类型或相反导电类型的杂质。

10. 发明授权

US08552775B2 Digital phase-locked loop apparatus using frequency shift keying and method of controlling the same 失效
标题翻译：使用频移键控的数字锁相环装置及其控制方法
公开(公告)号：US08552775B2
公开(公告)日：2013-10-08
申请号：US13589629
申请日：2012-08-20
申请人： Seung Sik Lee , Sangsung Choi , Young Ae Jeon , Sangjae Lee , Byoung Hak Kim , Mi Kyung Oh , Cheol-ho Shin , Kang-yoon Lee , YoungGun Pu , Joon-Sung Park
发明人： Seung Sik Lee , Sangsung Choi , Young Ae Jeon , Sangjae Lee , Byoung Hak Kim , Mi Kyung Oh , Cheol-ho Shin , Kang-yoon Lee , YoungGun Pu , Joon-Sung Park
IPC分类号： H03L7/06
CPC分类号： H03L7/0992
摘要： A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.
摘要翻译：使用FSK的数字锁相环装置包括PFD检测参考时钟和分频信号之间的相位差，以及第一加法器，用于通过将第一数字码，第二数字码和频道频率码相加来产生第一数字控制码包括彼此的信道信息，所述第一数字码从第一和第二脉冲之间的时间差转换。该装置还包括校正第一数字控制码的误差以产生第二数字控制码的数字滤波器，用于根据第二数字控制码根据数字调谐字改变振荡频率的DCO，以及双模分割单元将振荡频率分频成分频信号。

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