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1. 发明申请

US20080049412A1 HOLDER DEVICE FOR ANALYZING CHARACTERISTICS OF DOSIMETER 有权
标题翻译：用于分析剂量特性的支架装置
公开(公告)号：US20080049412A1
公开(公告)日：2008-02-28
申请号：US11775881
申请日：2007-07-11
申请人： Tae Suk Suh , Jin Beom CHUNG , Jeong Woo LEE , Yon Lae KIM , Kyoung Sik CHOI , Seoung Jong OH , Jai Woong YOON
发明人： Tae Suk Suh , Jin Beom CHUNG , Jeong Woo LEE , Yon Lae KIM , Kyoung Sik CHOI , Seoung Jong OH , Jai Woong YOON
IPC分类号： H05K5/00
CPC分类号： G01T1/02
摘要： Provided is a holder device for analyzing characteristics of a dosimeter. In the holder device, the dosimeter is located in a desired direction on a radiation path along which radiation is irradiated from a radiation emitter, and a radiation absorbance characteristic is recognized according to a radiation dose absorbed by the dosimeter. The holder device includes: a dosimeter holder fixedly supporting the dosimeter; a body having a partial spherical portion with a specific curvature, and having a plurality of mounting holes containing the dosimeter holder; and a supporter supporting the body so that the dosimeter is located on the radiation path. Accordingly, in the holder device for analyzing characteristics of a dosimeter, one or more dosimeters can be disposed at a desired angle and position with respect to a radiation emitter, characteristics of the dosimeter can be accurately analyzed, and thus radiation treatment and treatment schedule can be effectively performed.
摘要翻译：提供了一种用于分析剂量计的特性的保持装置。在保持器装置中，剂量计位于从辐射发射器照射辐射的辐射路径上的期望方向上，并且根据剂量计吸收的辐射剂量识别辐射吸收特性。支架装置包括：固定地支撑剂量计的剂量计支架; 具有具有特定曲率的部分球形部分的主体，并且具有容纳所述剂量计保持器的多个安装孔; 以及支撑身体的支撑件，使得剂量计位于辐射路径上。因此，在用于分析剂量计的特性的保持装置中，可以将一个或多个剂量计相对于辐射发射器设置在期望的角度和位置，可以准确地分析剂量计的特性，因此辐射治疗和治疗计划可以有效地执行。

2. 发明申请

US20090115496A1 VPP VOLTAGE GENERATOR FOR GENERATING STABLE VPP VOLTAGE 失效
标题翻译： VPP电压发生器，用于产生稳定的VPP电压
公开(公告)号：US20090115496A1
公开(公告)日：2009-05-07
申请号：US12341868
申请日：2008-12-22
申请人： Jeong Woo LEE
发明人： Jeong Woo LEE
IPC分类号： G05F1/10
CPC分类号： H02M3/07
摘要： The present invention relates to a VPP voltage generator that generates a stable VPP voltage. The VPP voltage generator of the present invention generates a stable VPP voltage. Therefore, power consumption can be saved, a precharge time of word line can be prevented from increasing and a tRCD characteristic can be improved. It is thus possible to improve the operational performance of semiconductor memory devices.
摘要翻译：本发明涉及产生稳定的VPP电压的VPP电压发生器。本发明的VPP电压发生器产生稳定的VPP电压。因此，可以节省功耗，可以防止字线的预充电时间增加，并且可以提高tRCD特性。因此可以提高半导体存储器件的操作性能。

3. 发明申请

US20130094317A1 REFRESH CONTROL CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS 审中-公开
标题翻译：冷却控制电路和半导体器件的方法
公开(公告)号：US20130094317A1
公开(公告)日：2013-04-18
申请号：US13602066
申请日：2012-08-31
申请人： Jeong Woo LEE
发明人： Jeong Woo LEE
IPC分类号： G11C11/402
CPC分类号： G11C11/40618
摘要： A refresh control circuit of a semiconductor apparatus includes: a first bank refresh counter configured to increase or decrease a logic value of a first refresh address signal when a first bank address signal is enabled during a refresh operation, a second bank refresh counter configured to increase or decrease a logic value of a second refresh address signal when a second bank address signal is enabled during the refresh operation, a bank selection unit configured to generate first and second bank select signals in response to the first and second bank address signals during the refresh operation, and a row selection unit configured to generate first and second row select signals in response to the first and second refresh address signals and the first and second bank select signals.
摘要翻译：半导体装置的刷新控制电路包括：第一存储体刷新计数器，被配置为当刷新操作期间启用第一存储体地址信号时增加或减少第一刷新地址信号的逻辑值，第二存储体刷新计数器被配置为增加或者在刷新操作期间启用第二存储体地址信号时减小第二刷新地址信号的逻辑值;存储体选择单元，被配置为在刷新期间响应于第一和第二存储区地址信号产生第一和第二存储体选择信号操作和行选择单元，被配置为响应于第一和第二刷新地址信号以及第一和第二存储体选择信号而产生第一和第二行选择信号。

4. 发明申请

US20070226403A1 COMPUTER STORAGE CONTROL 有权
标题翻译：计算机存储控制
公开(公告)号：US20070226403A1
公开(公告)日：2007-09-27
申请号：US11689129
申请日：2007-03-21
申请人： Sung-ho SON , Jeong Woo LEE
发明人： Sung-ho SON , Jeong Woo LEE
IPC分类号： G06F12/00 , G06F1/32
CPC分类号： G06F12/06 , G06F1/3221 , G06F1/3225 , G06F1/3275 , G06F3/0625 , G06F3/0644 , G06F3/0679 , G06F2212/1028 , G06F2212/2022 , Y02D10/13 , Y02D10/14 , Y02D10/154
摘要： A flash memory-based storage grouped into memory regions is controlled by determining whether the flash memory is accessed or not. Power to a first of the memory regions is controlled according to the determination result. Power to a second of the memory regions is controlled according to the determination result. Controlling includes enabling provision of power to the first memory region while concurrently denying power to the second memory region.
摘要翻译：分组到存储器区域的基于闪速存储器的存储器通过确定是否访问闪速存储器来控制。根据确定结果控制对第一存储区域的功率。根据确定结果控制对存储区域的第二个的电力。控制包括能够向第一存储器区域提供电力，同时拒绝对第二存储器区域的电力。

5. 发明申请

US20150026449A1 METHOD OF MANAGING A SOLID STATE DRIVE, ASSOCIATED SYSTEMS AND IMPLEMENTATIONS 审中-公开
标题翻译：管理固态驱动，相关系统和实现的方法
公开(公告)号：US20150026449A1
公开(公告)日：2015-01-22
申请号：US14508393
申请日：2014-10-07
申请人： Jin Gyu HEO , Donggi LEE , Seongsik HWANG , Dongjin LEE , Jeong Woo LEE , Wonmoon CHEON , Seungho LIM , Jong-Min KIM , Jae-Hwa LEE , Haeri LEE , Woonhyug JEE
发明人： Jin Gyu HEO , Donggi LEE , Seongsik HWANG , Dongjin LEE , Jeong Woo LEE , Wonmoon CHEON , Seungho LIM , Jong-Min KIM , Jae-Hwa LEE , Haeri LEE , Woonhyug JEE
IPC分类号： G06F9/44
CPC分类号： G06F9/4403 , G06F9/4406 , G06F12/0246 , G06F13/1673 , G06F2212/7201 , Y02D10/13 , Y02D10/14
摘要： One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system.
摘要翻译：方法的一个实施例包括在计算系统的初始化操作期间由存储器控制器将启动映像从固态驱动器加载到计算系统的操作存储器。初始化操作初始化计算系统的组件。

6. 发明申请

US20130176044A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130176044A1
公开(公告)日：2013-07-11
申请号：US13600177
申请日：2012-08-30
申请人： Jeong Woo LEE
发明人： Jeong Woo LEE
IPC分类号： G01R31/3187
CPC分类号： G01R31/31723
摘要： A semiconductor apparatus includes a control chip including a first selection unit configured to output one of signals which are inputted through a first normal port and a shared test port, in response to a test mode signal; and a second selection unit configured to output one of signals which are inputted through a second normal port and the shared test port, in response to the test mode signal, wherein the control chip is configured to transmit an output of the first selection unit to a first chip and transmit an output of the second selection unit to a second chip.
摘要翻译：一种半导体装置，包括：控制芯片，包括：第一选择单元，被配置为响应于测试模式信号输出通过第一正常端口和共享测试端口输入的信号之一; 以及第二选择单元，被配置为响应于测试模式信号输出通过第二正常端口和共享测试端口输入的信号之一，其中控制芯片被配置为将第一选择单元的输出发送到第一芯片并将第二选择单元的输出发送到第二芯片。

7. 发明申请

US20130094316A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20130094316A1
公开(公告)日：2013-04-18
申请号：US13340868
申请日：2011-12-30
申请人： Sang Hoon SHIN , Hyung Dong LEE , Jeong Woo LEE , Young Suk MOON
发明人： Sang Hoon SHIN , Hyung Dong LEE , Jeong Woo LEE , Young Suk MOON
IPC分类号： G11C11/402
CPC分类号： G11C11/40603 , G11C11/40611 , G11C11/40615
摘要： A memory system includes: a controller configured to provide a hidden auto refresh command; and a memory configured to perform a refresh operation in response to the hidden auto refresh command. The controller and the memory communicate with each other so that each refresh address of the controller and the memory has the same value as each other.
摘要翻译：存储器系统包括：控制器，被配置为提供隐藏的自动刷新命令; 以及被配置为响应于所述隐藏的自动刷新命令执行刷新操作的存储器。控制器和存储器彼此通信，使得控制器和存储器的每个刷新地址彼此具有相同的值。

8. 发明申请

US20110024743A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20110024743A1
公开(公告)日：2011-02-03
申请号：US12648680
申请日：2009-12-29
申请人： Jeong Woo LEE , Hyung Dong Lee , Jun Gi Choi , Sang Hoon Shin , Xiang Hua Cui
发明人： Jeong Woo LEE , Hyung Dong Lee , Jun Gi Choi , Sang Hoon Shin , Xiang Hua Cui
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , G01R31/2884 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.
摘要翻译：半导体集成电路包括具有多个半导体芯片的多芯片封装。半导体集成电路包括信号线; 以及多个半导体芯片中的半导体芯片中的信号负载补偿部，被配置为响应于测试信号的激活而将设计的信号加载到信号线。这里，设计的信号负载具有与信号线的多个半导体芯片中的另一半导体芯片的信号负载分量相对应的值。

9. 发明申请

US20130176764A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20130176764A1
公开(公告)日：2013-07-11
申请号：US13601552
申请日：2012-08-31
申请人： Jeong Woo LEE
发明人： Jeong Woo LEE
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , H01L25/0655 , H01L2224/16225 , H01L2924/15192 , H01L2924/15311
摘要： A semiconductor apparatus includes a controller, a memory, a normal line, a test line, and a path setting unit. The normal line is provided for communication between the controller and the memory. The test line is provided for a test operation of the memory. The path setting unit connects either the normal line or the test line to the memory according to a type of access mode.
摘要翻译：半导体装置包括控制器，存储器，法线，测试线和路径设定单元。为控制器与存储器之间的通讯提供法线。提供测试线用于存储器的测试操作。路径设置单元根据访问模式的类型将法线或测试线连接到存储器。

10. 发明申请

US20080080616A1 APPARATUS AND METHOD FOR COMPRESSION-ENCODING MOVING PICTURE 有权
标题翻译：用于压缩编码移动图像的装置和方法
公开(公告)号：US20080080616A1
公开(公告)日：2008-04-03
申请号：US11774948
申请日：2007-07-09
申请人： Jin Wuk SEOK , Chang Sik CHO , Jeong Woo LEE
发明人： Jin Wuk SEOK , Chang Sik CHO , Jeong Woo LEE
IPC分类号： H04N7/50
CPC分类号： H04N19/107 , H04N19/109 , H04N19/11 , H04N19/14 , H04N19/147 , H04N19/176 , H04N19/61
摘要： Provided are an apparatus and method for compression-encoding a moving picture at high speed while minimizing image quality deterioration. In H.264 moving picture encoding, the apparatus and method perform rate-distortion optimization (RDO) indispensable for high-definition encoding by feedback prediction, and minimize the amount of discrete cosine transform (DCT)-inverse DCT (IDCT) calculation performed for RDO many times, thereby performing H.264 encoding at high speed.The apparatus includes: a B-slice checker for performing a B-slice check for current frame data; a maximum inter mode prediction bit calculator for performing motion estimation and motion compensation for an inter mode using the maximum division block and calculating a prediction bit value; a minimum intra mode prediction bit calculator for performing motion estimation and motion compensation for an intra mode using the minimum division block and calculating a prediction bit value; a linear prediction bit estimator for calculating prediction bit values for modes other than the inter mode using the maximum division block and the intra mode using the minimum division block, using linear parameters and stochastic values; a mode determiner for comparing the prediction bit values calculated by the maximum inter mode prediction bit calculator, the minimum intra mode prediction bit calculator and the linear prediction bit estimator and determining an appropriate encoding mode; and an encoder for encoding the current frame data in the mode determined by the mode determiner.
摘要翻译：提供了一种用于在运动图像高速压缩编码同时最小化图像质量劣化的装置和方法。在H.264运动图像编码中，该装置和方法通过反馈预测执行对于高清晰度编码不可缺少的速率失真优化（RDO），并且最小化离散余弦变换（DCT）逆DCT（IDCT）计算量 RDO多次，从而高速执行H.264编码。该装置包括：B片检查器，用于对当前帧数据执行B片检查; 最大帧间模式预测比特计算器，用于使用最大分割块对帧间模式进行运动估计和运动补偿，并计算预测比特值; 最小帧内模式预测比特计算器，用于使用最小分割块对帧内模式进行运动估计和运动补偿，并计算预测比特值; 线性预测比特估计器，用于使用线性参数和随机值，使用最大分割块和使用最小分割块的帧内模式来计算除了帧间模式以外的模式的预测比特值; 模式确定器，用于比较由最大帧间模式预测比特计算器，最小帧内模式预测比特计算器和线性预测比特估计器计算的预测比特值，并确定适当的编码模式; 以及编码器，用于以由模式确定器确定的模式对当前帧数据进行编码。

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