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    • 7. 发明授权
    • Signal processing apparatus including plural aggregates
    • 信号处理装置包括多个聚集体
    • US5581662A
    • 1996-12-03
    • US441418
    • 1995-05-15
    • Toshiyuki FurutaHiroyuki HoriguchiHirotoshi EguchiYutaka EbiTatsuya FurukawaYoshio WatanabeToshihiro Tsukagoshi
    • Toshiyuki FurutaHiroyuki HoriguchiHirotoshi EguchiYutaka EbiTatsuya FurukawaYoshio WatanabeToshihiro Tsukagoshi
    • G06N3/063G06F15/18
    • G06N3/063
    • A hierarchical signal processing apparatus includes aggregates having logic operation portions. The apparatus compares a final output signal from a logic operation portion in a final aggregate with a teaching signal, and generates an error signal by taking a signal which exists only in the teaching signal as a positive error signal, and taking a signal which exists only in said final output signal as a negative error signal. An error signal generating portion in the apparatus generates a positive error signal of a logic operating portion within a certain aggregate which supplies one or more output signals thereof to said logic operation means of another aggregate based on one or more logic operations on the excitatory weight function signal of said weight function signal, the positive error signal, the inhibitory weight function signal of said weight function signal and the negative error signal, and also generates a negative error signal of said logic operation means within said certain aggregate which supplies one or more output signals thereof to said logic operation means of said other aggregate based on one or more logic operations on the inhibitory weight function signal of said weight function signal, the positive error signal of said other aggregate, the excitatory weight function signal of said weight function signal and the negative error signal.
    • 分级信号处理装置包括具有逻辑运算部分的聚合。 该装置将来自最终聚合中的逻辑运算部分的最终输出信号与示教信号进行比较,并且通过仅将在教学信号中存在的信号作为正误差信号,并且仅采用仅存在的信号来产生误差信号 在所述最终输出信号中作为负误差信号。 该装置中的误差信号产生部分产生一定聚集内的逻辑运算部分的正误差信号,该积分误差信号基于对兴奋性加权函数的一个或多个逻辑运算向另一聚合体的一个或多个输出信号提供一逻辑运算装置 所述加权函数信号的信号,正误差信号,所述加权函数信号的抑制加权函数信号和负误差信号,并且还产生所述逻辑运算装置的负误差信号,所述负误差信号提供一个或多个输出 基于对所述加权函数信号的抑制加权函数信号,所述另一聚合体的正误差信号,所述加权函数信号的兴奋度权重函数信号和所述加权函数信号的抑制加权函数信号的一个或多个逻辑运算, 负误差信号。
    • 9. 发明授权
    • Neuron unit and neuron unit network
    • 神经元单位和神经元单位网络
    • US5131073A
    • 1992-07-14
    • US550404
    • 1990-07-10
    • Toshiyuki FurutaHiroyuki HoriguchiHirotoshi Eguchi
    • Toshiyuki FurutaHiroyuki HoriguchiHirotoshi Eguchi
    • G06N3/063
    • G06N3/063
    • A neuron unit simultaneously processes a plurality of binary input signals. The neuron unit includes input lines for receiving first and second input signals which undergo transitions with time, first and second memories for storing weighting coefficients, a first gate for successively obtaining a logical product of one of the first input signals and a corresponding one of the weighting coefficients read out from the first memory for each of the first input signals, a second gate for successively obtaining a logical product of one of the second input signals and a corresponding one of the weighting coefficients read out from the second memory for each of the second input signals, a third gate for obtaining a logical sum of logical products output from the first gate, a fourth gate for obtaining a logical sum of logical products output from the second gate, and an output part including an inverter for inverting the logical sum output from the fourth gate and a gate for obtaining one of a logical product and a logical sum of the logical sum output from the third gate and an inverted logical sum output from the inverter. This gate outputs an output signal of the neuron unit.
    • 神经元单元同时处理多个二进制输入信号。 神经元单元包括输入线,用于接收经历时间转变的第一和第二输入信号,用于存储加权系数的第一和第二存储器,用于连续获得第一输入信号之一和 对于每个第一输入信号从第一存储器读出的加权系数,第二门,用于连续地获得第二输入信号中的一个的逻辑积和从第二存储器读出的对应的一个加权系数 第二输入信号,用于获得从第一门输出的逻辑积的逻辑和的第三门,用于获得从第二门输出的逻辑积的逻辑和的第四门和包括用于反转逻辑和的反相器的输出部 从第四门输出的门和用于获得从第三门的逻辑和输出的逻辑积和逻辑和之一的门 门和反相逻辑和输出。 该门输出神经元单元的输出信号。