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1. 发明授权

US4688193A Bit processing utilizing a row and column ladder sequence 失效
标题翻译：利用行和列梯形图序列进行位处理
公开(公告)号：US4688193A
公开(公告)日：1987-08-18
申请号：US635153
申请日：1984-07-27
申请人： Hiromasa Yamaoka , Tadashi Okamoto , Yuzaburo Iwasa , Kouichi Kimura
发明人： Hiromasa Yamaoka , Tadashi Okamoto , Yuzaburo Iwasa , Kouichi Kimura
IPC分类号： G06F9/32 , G05B19/05 , G06F9/30 , G06F9/00
CPC分类号： G05B19/05 , G05B2219/1172 , G05B2219/13082
摘要： A relay ladder sequence circuitry having i columns and j rows is divided into a plurality of sections each having a predetermined number of rows, and the bit informations are processed in a parallel manner in the rows of the sections. More specifically, the program in accordance with the sequence ladder construction is memorized and are successively read out as the addresses of the program are appointed. The signals of relay contacts as the bit information are processed for each line in accordance with the read out program, so that a high processing speed is attained.
摘要翻译：具有i列和j行的梯形图梯形序列电路被分成多个部分，每个部分具有预定数量的行，并且位部信息以并行方式处理在这些部分的行中。更具体地说，根据序列梯形结构的程序被记忆并随着程序的地址被指定而连续读出。根据读出程序，为每行处理作为位信息的继电器触点的信号，从而达到高处理速度。

2. 发明授权

US5504673A Microprogram load unit 失效
标题翻译：微程序负载单元
公开(公告)号：US5504673A
公开(公告)日：1996-04-02
申请号：US246721
申请日：1994-05-20
申请人： Tadashi Okamoto , Hiromasa Yamaoka , Kazuhiko Shimoyama
发明人： Tadashi Okamoto , Hiromasa Yamaoka , Kazuhiko Shimoyama
IPC分类号： G06F9/22 , G06F9/24 , G06F9/445 , G06F19/00 , G06F12/16
CPC分类号： G06F9/24
摘要： A microprogram load unit comprising a readable and writable microprogram memory within a central processor unit for storing microprogram, a relatively low speed, readable and writable, nonvolatile memory unit, and a readable and writable memory with battery backup. It is determined whether data of the readable and writable memory with backup has been lost or not when power is turned on. If data loss is not present, microprogram is read out of the readable and writable memory with backup and written into the microprogram memory. If data loss is present, microprogram is read out of the nonvolatile memory unit and is written into the microprogram memory.
摘要翻译：微程序加载单元包括用于存储微程序的中央处理器单元中的可读写可编程微程序存储器，相对低速，可读和可写的非易失性存储器单元以及具有电池备份的可读写可用存储器。在打开电源时，确定具有备份的可读写可写存储器的数据是否已丢失。如果不存在数据丢失，则通过备份和写入微程序存储器，从可读写的存储器中读出微程序。如果存在数据丢失，则从非易失性存储器单元中读出微程序，并写入微程序存储器。

3. 发明授权

US4628436A Digital controller 失效
标题翻译：数字控制器
公开(公告)号：US4628436A
公开(公告)日：1986-12-09
申请号：US582541
申请日：1984-02-22
申请人： Tadashi Okamoto , Hiromasa Yamaoka
发明人： Tadashi Okamoto , Hiromasa Yamaoka
IPC分类号： G06F15/16 , G05B19/05 , G06F9/00 , G06F9/38 , G06F9/46 , G06F12/00 , G06F15/80
CPC分类号： G06F9/3824
摘要： A digital controller for controlling a plurality of processes. In view of the fact that in case a plurality of processes of a like nature are to be controlled, same operands are used for performing a similar arithmetic operation a number of times, instructions are stored in a common memory for simplifying the programming, while the operands are stored in memories each incorporated in each of the processors adapted for controlling individually the objective processes, to thereby allow arithmetic processings to be performed by the processors in parallel with one another. Overall processing speed is made thus significantly high.
摘要翻译：一种用于控制多个处理的数字控制器。考虑到在要控制多个相同性质的处理的情况下，使用相同的操作数来执行多次相似的算术运算，指令被存储在公共存储器中以简化编程，而操作数存储在各自并入每个处理器的存储器中，适用于单独控制目标处理，从而允许由处理器彼此并行执行算术处理。因此，总体处理速度显着高。

4. 发明授权

US5237687A Microprogram load unit having alternative backup memory sources 失效
标题翻译：具有备用备份存储源的微处理器负载单元
公开(公告)号：US5237687A
公开(公告)日：1993-08-17
申请号：US768322
申请日：1985-08-22
申请人： Tadashi Okamoto , Hiromasa Yamaoka , Kazuhiko Shimoyama
发明人： Tadashi Okamoto , Hiromasa Yamaoka , Kazuhiko Shimoyama
IPC分类号： G06F9/22 , G06F9/24 , G06F9/445
CPC分类号： G06F9/24
摘要： A microprogram load unit comprising a readable and writable microprogram memory within a central processor unit for storing microprogram, a relatively low speed, readable and writable, nonvolatile memory unit, and a readable and writable memory with battery backup. It is determined whether data of the readable and writable memory with backup has been lost or not when power is turned on. If data loss is not present, microprogram is read out of the readable and writable memory with backup and written into the microprogram memory. If data loss is present, microprogram is read out of the nonvolatile memory unit and is written into the microprogram memory.
摘要翻译：微程序加载单元包括用于存储微程序的中央处理器单元中的可读写可编程微程序存储器，相对低速，可读和可写的非易失性存储器单元以及具有电池备份的可读写可用存储器。在打开电源时，确定具有备份的可读写可写存储器的数据是否已丢失。如果不存在数据丢失，则通过备份和写入微程序存储器，从可读写的存储器中读出微程序。如果存在数据丢失，则从非易失性存储器单元中读出微程序，并写入微程序存储器。

5. 发明授权

US4694419A Programmable controller with direct to plant addressing 失效
标题翻译：可编程控制器，直接到工厂寻址
公开(公告)号：US4694419A
公开(公告)日：1987-09-15
申请号：US658025
申请日：1984-10-05
申请人： Tadashi Okamoto , Kazuhiko Shimoyama , Hiromasa Yamaoka , Mitsuro Takakura
发明人： Tadashi Okamoto , Kazuhiko Shimoyama , Hiromasa Yamaoka , Mitsuro Takakura
IPC分类号： G05B19/05 , G06F9/32 , G06F9/35 , G06F9/355 , G05B11/01 , G06F9/34
CPC分类号： G06F9/355 , G05B19/05 , G06F9/35 , G05B2219/15105
摘要： A programmable controller for controlling a plant on the basis of a stored program includes a processing unit for reading out an instruction from a program memory to process the instruction. In the processing unit, it is determined whether the instruction read out from the memory is an instruction taking a register-modified addressing mode or an instruction taking a direct addressing mode. When the read-out instruction is an instruction taking the direct addressing mode, a plant is directly addressed by the address part of the instruction. Then, an arithmetic operation is performed using the state information which is read out from the plant thus addressed, or plant control information is sent from the processing unit to the plant thus addressed.
摘要翻译：一种用于基于存储的程序控制工厂的可编程控制器包括一个处理单元，用于从程序存储器读出指令以处理该指令。在处理单元中，确定从存储器读出的指令是否是采用寄存器修改寻址模式的指令或采用直接寻址模式的指令。当读出指令是采用直接寻址模式的指令时，工厂由指令的地址部分直接寻址。然后，使用从这样寻址的工厂读出的状态信息进行算术运算，或者从处理单元将工厂控制信息发送到如此寻址的设备。

6. 发明授权

US5410470A Process control method and system with employment of fuzzy inference 失效
标题翻译：使用模糊推理的过程控制方法和系统
公开(公告)号：US5410470A
公开(公告)日：1995-04-25
申请号：US57997
申请日：1993-05-05
申请人： Hiromasa Yamaoka , Mitsuaki Kobayashi , Yasuhiro Tennichi , Tadayoshi Saito
发明人： Hiromasa Yamaoka , Mitsuaki Kobayashi , Yasuhiro Tennichi , Tadayoshi Saito
IPC分类号： G05B13/02 , G05B13/04 , G05D9/12 , G06F15/46
CPC分类号： G05B13/0275 , Y10S706/90
摘要： A process control method and a process control apparatus using a fuzzy control with reducing rules and membership functions. The process control apparatus for determining a manipulating variable of a controlled object, includes an input/output unit for inputting a present value of a controlled variable and for outputting the determined manipulating variable, a predicting unit having a simulator of a controlled object, for calculating a control variable after a predetermined time has passed, assuming now that a present value of the manipulating variable is continued, and a fuzzy controlling unit for inferring a manipulating variable at a present time by inputting a deviation value between a preset set-point value and a predicted value. The simulator simulates the controlled object as dead time and a first order delay. Since only the predicted value of the controlled variable is employed as the input of the fuzzy control, fuzzy inference can be simplified and noise resistance can be improved.
摘要翻译：一种使用具有减少规则和隶属函数的模糊控制的过程控制方法和过程控制装置。用于确定受控对象的操作变量的过程控制装置包括输入/输出单元，用于输入受控变量的当前值并输出所确定的操作变量，具有受控对象的模拟器的预测单元，用于计算假定现在操作变量的当前值继续在经过预定时间之后的控制变量，以及模糊控制单元，用于通过在预设的设定点值和预测值。模拟器将受控对象模拟为死区时间和一阶延迟。由于仅采用控制变量的预测值作为模糊控制的输入，因此可以简化模糊推理，提高噪声抵抗。

7. 发明授权

US5796936A Distributed control system in which individual controllers executed by sharing loads 失效
标题翻译：通过共享负载执行单个控制器的分布式控制系统
公开(公告)号：US5796936A
公开(公告)日：1998-08-18
申请号：US801923
申请日：1997-02-14
申请人： Mitsuru Watabe , Hiromasa Yamaoka
发明人： Mitsuru Watabe , Hiromasa Yamaoka
IPC分类号： G05B9/03 , G05B19/042 , G06F9/46 , G06F9/50 , G06F11/20 , G06F15/16 , G06F15/177 , H04L12/28 , G06F13/00
CPC分类号： G05B19/0428 , G05B2219/25232
摘要： A distributed control system includes a plurality of controllers each composed of a plurality of processors and being coupled through a network. Each controller includes a scheduler for measuring a load; internal backup means for controlling which controller bears the load; backup request means for requesting another controller to bear the load; and backup accept means for answering to a request for bearing the load from another controller in accordance with the load of the requesting controller. Thus, the load which cannot be executed by one controller can be distributed and executed by other controllers in accordance with their loads.
摘要翻译：分布式控制系统包括多个控制器，每个控制器由多个处理器组成并通过网络耦合。每个控制器包括用于测量负载的调度器; 用于控制哪个控制器负载的内部备份装置; 备用请求装置，用于请求另一控制器承担负载; 以及备份接受装置，用于根据请求控制器的负载应答来自另一控制器的负载请求。因此，不能由一个控制器执行的负载可以根据其负载由其他控制器分配和执行。

8. 发明授权

US5682466A Information processing apparatus for obtaining output data from plural sets of input and output data values 失效
标题翻译：信息处理装置，用于从多组输入和输出数据值获得输出数据
公开(公告)号：US5682466A
公开(公告)日：1997-10-28
申请号：US117765
申请日：1993-09-08
申请人： Akira Maeda , Motohisa Funabashi , Hiromasa Yamaoka , Nobuyuki Fujikura , Mikio Yoda , Mitsuo Yanagi
发明人： Akira Maeda , Motohisa Funabashi , Hiromasa Yamaoka , Nobuyuki Fujikura , Mikio Yoda , Mitsuo Yanagi
IPC分类号： G05B13/02 , G06K9/64 , G06F17/00
CPC分类号： G05B13/0275 , G06K9/64 , Y10S706/903
摘要： An information processing apparatus, which is easy to design and has functions of high speed processing, learning, and so on, includes a plurality of memories for storing sets of previously known input data (called response pattern data) and correct output data corresponding thereto; a comparator for providing input data supplied in actual operations to the plurality of sets and comparing the input data with the response pattern data in each set; an evaluation unit for evaluating the distance (degree of similarity) between the input data and the response pattern data; and a generator for generating final outputs by composing the evaluation result for each set and the output data in that set, for example, using a method which calculates weighted average values based on the evaluated distances.
摘要翻译：易于设计并具有高速处理，学习等功能的信息处理装置包括多个存储器，用于存储先前已知的输入数据（称为响应模式数据）和正确的对应的输出数据的集合; 比较器，用于将实际操作中提供的输入数据提供给多个组，并将输入数据与每组中的响应模式数据进行比较; 评估单元，用于评估输入数据和响应模式数据之间的距离（相似度）; 以及发生器，用于通过组合各组的评估结果和该组中的输出数据来生成最终输出，例如使用基于评估的距离来计算加权平均值的方法。

9. 发明授权

US4494113A Method and apparatus for self-control in distributed priority collision 失效
标题翻译：分布式优先级碰撞中自我控制的方法和装置
公开(公告)号：US4494113A
公开(公告)日：1985-01-15
申请号：US356891
申请日：1982-03-10
申请人： Hiromasa Yamaoka , Yuzaburo Iwasa , Kazuhisa Matunaga
发明人： Hiromasa Yamaoka , Yuzaburo Iwasa , Kazuhisa Matunaga
IPC分类号： G06F13/26 , G06F13/372 , H04L12/413 , H04Q9/00
CPC分类号： H04L12/413 , G06F13/26 , G06F13/372
摘要： Method and apparatus for controlling collision in a system having a common unit shared by a plurality of devices are disclosed. More particularly, method and apparatus for controlling priority collision in a system where a computer is shared by a plurality of terminal devices or a memory unit is shared by a plurality of computers are disclosed. Continued time period of non-access to the common unit by any of the plurality of devices is measured in each of the plurality of devices, and when the measured time period coincides with one of preset time periods inherently assigned to the respective devices, the associated one of the plurality of devices is permitted to access to the common unit on the condition that the common unit is not busy and that one device issues an access request to the common unit. In addition to ordinary access request to the common unit, a priority interruption access request may be issued.
摘要翻译：公开了一种用于控制具有由多个设备共享的公共单元的系统中的冲突的方法和装置。更具体地，公开了一种用于控制由多个终端设备或存储器单元共享计算机的系统中的优先级冲突的方法和装置，由多台计算机共享。在多个设备中的每个设备中测量在多个设备中的任一个中不访问公共单元的持续时间段，并且当测量的时间段与固有地分配给各个设备的预设时间段中的一个一致时，相关联的允许多个设备中的一个在公共单元不忙并且一个设备向公共单元发出访问请求的情况下访问公共单元。除了对公共单元的普通访问请求之外，还可以发出优先中断访问请求。

10. 发明授权

US5638492A Information processing apparatus and monitoring apparatus 失效
标题翻译：信息处理装置和监视装置
公开(公告)号：US5638492A
公开(公告)日：1997-06-10
申请号：US291869
申请日：1994-08-17
申请人： Akira Maeda , Motohisa Funabashi , Hiromasa Yamaoka , Nobuyuki Fujikura , Mikio Yoda , Mitsuo Yanagi , Toshihide Ichimori
发明人： Akira Maeda , Motohisa Funabashi , Hiromasa Yamaoka , Nobuyuki Fujikura , Mikio Yoda , Mitsuo Yanagi , Toshihide Ichimori
IPC分类号： G05B13/02 , G06K9/64 , G06F17/00
CPC分类号： G06K9/64 , G05B13/0285 , F02D41/1405 , Y10S706/903
摘要： An information processing apparatus is capable of achieving high-level functions such as high-speed processing and learning without requiring a complex algorithm based on, for example, knowledge processing. A plurality of sets of known input data and correct output data corresponding thereto are beforehand stored. The stored input data is called response pattern data. Data actually inputted in the system operation is supplied to the plural sets of data. For each set of data, the input data is compared with the response pattern data to evaluate a distance (degree of similarity) therebetween. Results of evaluations for the respective sets of data are combined with the associated output data, for example, according to weighted average values on the basis of the evaluated distance, thereby generating final outputs.
摘要翻译：信息处理装置能够实现诸如高速处理和学习的高级功能，而不需要基于例如知识处理的复杂算法。预先存储多组已知的输入数据和与之对应的正确的输出数据。存储的输入数据称为响应模式数据。在系统操作中实际输入的数据被提供给多组数据。对于每组数据，将输入数据与响应模式数据进行比较，以评估它们之间的距离（相似度）。将各组数据的评估结果与相关的输出数据组合，例如根据所评估距离的加权平均值，从而产生最终输出。

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