专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4665478A Computer system 失效
标题翻译：电脑系统
公开(公告)号：US4665478A
公开(公告)日：1987-05-12
申请号：US640568
申请日：1984-08-14
申请人： Tadashi Hirose , Kousuke Sakoda , Tomihiko Kojima , Hidehiko Akita , Tsutomu Miyairi
发明人： Tadashi Hirose , Kousuke Sakoda , Tomihiko Kojima , Hidehiko Akita , Tsutomu Miyairi
IPC分类号： G06F11/32 , G06F3/023 , G06F3/048 , G06F13/00 , G06F15/00 , G06F3/00
CPC分类号： G06F3/0489
摘要： A computer system comprises a memory for storing communication history information between a terminal and an execution program, and an output message file for storing sets of communication history conditions and output messages corresponding to those conditions. When the terminal issues a message output request, only the output message that meets the communication history condition is selected from the output message file and outputted to the terminal.
摘要翻译：计算机系统包括用于存储终端和执行程序之间的通信历史信息的存储器，以及用于存储与这些条件相对应的通信历史条件和输出消息的组的输出消息文件。当终端发出消息输出请求时，仅从输出消息文件中选择满足通信历史条件的输出消息并将其输出到终端。

2. 发明授权

US4692896A Method of processing a plurality of code systems 失效
标题翻译：处理多个代码系统的方法
公开(公告)号：US4692896A
公开(公告)日：1987-09-08
申请号：US752853
申请日：1985-07-08
申请人： Kousuke Sakoda , Masahiro Kainaga , Hidehiko Akita , Fumiya Murata , Yoshitake Nakaosa
发明人： Kousuke Sakoda , Masahiro Kainaga , Hidehiko Akita , Fumiya Murata , Yoshitake Nakaosa
IPC分类号： G06F3/00 , G06F3/01 , G06F5/00 , G06F9/45
CPC分类号： G06F3/018 , G06F5/00
摘要： A method of processing a plurality of different code systems for an information processing apparatus including an operating system, comprises a step of inputting a source program, and a compiling step of analyzing meaning of the source program to thereby create a series of instructions and data required for executing a processing equivalent to the meaning of the source program. The compiling step includes a sub-step of transforming character type constants to a first code system occupying region including a first number of bits and transforming character string constants to a second code system occupying a region including a number of bits which is equal to product of a sum of the number of characters of the character string constants plus one and multiplied with the first bit number so that character type variables designated in the source program correspond, respectively, to the region of the first bit number while a character type array corresponds to a region including a number of bits which is equal to a product resulting from multiplication of the first bit number with the number of elements of the array.
摘要翻译：一种用于处理包括操作系统的信息处理设备的多个不同代码系统的方法，包括输入源程序的步骤和分析源程序的含义的编译步骤，从而创建一系列指令和数据用于执行等同于源程序含义的处理。编译步骤包括将字符类型常数转换为包括第一位数的第一代码系统占用区和将字符串常数变换到占用包括多个位的位的区域的第二代码系统的子步骤，该位数等于字符串常数加1的字符数与乘以第一位数的字符数之和，使得在源程序中指定的字符类型变量分别对应于第一位数的区域，而字符类型数组对应于包括多个比特的区域，该比特数等于由第一比特数乘以阵列的元素的数目而产生的乘积。

3. 发明授权

US4794528A Pattern matching method for tree structured data 失效
标题翻译：树结构数据的模式匹配方法
公开(公告)号：US4794528A
公开(公告)日：1988-12-27
申请号：US15111
申请日：1987-02-17
申请人： Tadashi Hirose , Kazuo Nakao , Kousuke Sakoda , Youichi Takeuchi
发明人： Tadashi Hirose , Kazuo Nakao , Kousuke Sakoda , Youichi Takeuchi
IPC分类号： G06F9/44 , G06F17/30 , G06F1/00
CPC分类号： G06F8/3135 , G06F17/30985 , Y10S707/99936 , Y10S707/99942
摘要： In order to highly speed up the pattern matching of tree structured data in a logic programming language, the priority order is set when the data owned by the individual nodes of a tree structure are to be transversely sought, and the tree structured data are expressed in a vector type, in which they are arranged in that priority order, so that they are compared consecutively from the head for each element of the vector.
摘要翻译：为了以逻辑编程语言高度加速树结构化数据的模式匹配，当要横向寻求树结构的各个节点所拥有的数据时，设置优先顺序，并将树结构化数据表示为一种向量类型，它们按照该优先级顺序排列，从而从矢量的每个元素的头部连续进行比较。

4. 发明授权

US5043873A Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems 失效
标题翻译：并行处理方法，用于避免共享内存系统中常见的竞争控制问题和数据上传问题
公开(公告)号：US5043873A
公开(公告)日：1991-08-27
申请号：US395444
申请日：1989-08-17
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data. Concurrently and in parallel with the execution of the task program, the data is transmitted to each of the elemental processors that are awaiting the data with only a write instruction and without any communications instruction.

5. 发明授权

US4951193A Parallel computer with distributed shared memories and distributed task activating circuits 失效
标题翻译：具有分布式共享存储器和分布式任务激活电路的并行计算机
公开(公告)号：US4951193A
公开(公告)日：1990-08-21
申请号：US85646
申请日：1987-08-14
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
摘要翻译：在访问存储器时，每个元件处理器执行构造成为每个元件处理器指定属于预定本地地址区域的地址的程序。当由元件处理器执行存储器写入指令时，检测由指令指定的存储器地址是否与预定地址一致。如果检测到，则属于另一元件处理器的本地地址空间并分配给首先提到的预定地址的预定地址以及响应写指令写入的数据被发送到另一元件处理器以指示数据为在其中写入作为复制数据。对于每个元件处理器独立地确定要执行的下一个任务。

6. 发明授权

US5485612A Method and apparatus for assigning processors in parallel computer system 失效
标题翻译：用于在并行计算机系统中分配处理器的方法和装置
公开(公告)号：US5485612A
公开(公告)日：1996-01-16
申请号：US830673
申请日：1992-02-04
申请人： Hiroshi Ota , Kousuke Sakoda , Tetsuo Saito , Eiichiro Maeda , Toshiyuki Yamamoto
发明人： Hiroshi Ota , Kousuke Sakoda , Tetsuo Saito , Eiichiro Maeda , Toshiyuki Yamamoto
IPC分类号： G06F9/44 , G06F9/45 , G06F15/16 , G06F15/177 , G06F13/00 , G06F7/38
CPC分类号： G06F8/456 , G06F8/45
摘要： A computer system has a plurality of processors, each having a local memory. An expression is represented by operands and operations and is expressed in a form of a tree. The operands are assigned to leaf nodes of the tree and the operations are assigned to interior nodes. Processors which store an operand represented by a leaf node are assigned to the leaf node. The tree is traced in a bottom-up fashion to determine a set of candidate processors to be assigned to each of the interior nodes. The candidate processors are determined from processors which are assigned to children nodes of each interior node in accordance with a majority method. The majority method is based on a rule that a processor which is most frequently assigned to the children nodes of an interior node is determined as a candidate processor. A root processor is assigned to a root node of the interior nodes from the candidate processors. The tree is then traced in a top-down fashion to determine definitely one processor to be assigned to each interior node from the candidate processors determined for the corresponding interior node.
摘要翻译：计算机系统具有多个处理器，每个处理器具有本地存储器。表达式由操作数和操作表示，并以树的形式表示。操作数分配给树的叶节点，并将操作分配给内部节点。存储由叶节点表示的操作数的处理器被分配给叶节点。树以自下而上的方式进行跟踪，以确定要分配给每个内部节点的一组候选处理器。根据多数方法，从分配给每个内部节点的子节点的处理器确定候选处理器。多数方法基于将内部节点的最常被分配给子节点的处理器确定为候选处理器的规则。根处理器从候选处理器分配给内部节点的根节点。然后以自顶向下的方式跟踪树，以确定从为相应的内部节点确定的候选处理器分配给每个内部节点的一个处理器。

7. 发明授权

US5293594A Data processing system having a plurality of register groups and a logical or circuit for addressing one register of one of the register groups 失效
标题翻译：具有多个寄存器组的数据处理系统和用于寻址一个寄存器组的一个寄存器的逻辑或电路
公开(公告)号：US5293594A
公开(公告)日：1994-03-08
申请号：US503626
申请日：1990-04-03
申请人： Tohru Nojiri , Shunpei Kawasaki , Tan Watanabe , Kousuke Sakoda
发明人： Tohru Nojiri , Shunpei Kawasaki , Tan Watanabe , Kousuke Sakoda
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0292
摘要： In order to divide a memory addressed unidimensionally into a plurality of memory areas and to manage efficiently these memory areas, the address to be accessed inside the memory is determined on a software basis by a computer instruction by use of the value of a first pointer designating each memory area and the value of a second pointer designating the relative address in the designated memory area.
摘要翻译：为了将被一维地寻址的存储器分割成多个存储区域并且有效地管理这些存储区域，存储器内部要访问的地址由软件基础上由计算机指令通过使用第一指针的值指定每个存储器区域和指定指定存储器区域中的相对地址的第二指针的值。

8. 发明授权

US4491912A Data processing system with improved microsubroutine facility 失效
标题翻译：数据处理系统具有改进的微型程序设施
公开(公告)号：US4491912A
公开(公告)日：1985-01-01
申请号：US358676
申请日：1982-03-16
申请人： Masahiro Kainaga , Kousuke Sakoda , Hiroaki Nakanishi
发明人： Masahiro Kainaga , Kousuke Sakoda , Hiroaki Nakanishi
IPC分类号： G06F9/22 , G06F9/26
CPC分类号： G06F9/265
摘要： A data processing system having a first storage for storing therein microprograms; an address register for supplying an instruction address of a microprogram to be executed into said first storage; a stack unit having a stack area for storing therein a return address of the microprogram; a first control unit responsive to a microinstruction for instructing a microsubroutine call to store the return address of the microinstruction in the stack unit, and responsive to a microinstruction for instructing return from the microsubroutine to restore the return address of the microinstruction from said stack unit; a second control unit for monitoring an interrupt request; a second storage for saving therein the content of said stack unit; a status register having a field for indicating the acceptance of the interrupt request in the course of the execution of the microprogram, and a third control unit responsive to the detection of the interrupt request by the second control unit in the course of the execution of the microprogram to indicate the acceptance of the interrupt request by the status register and save the content of the stack unit in said second storage, and responsive to the presence of the indication in the status register indicating the acceptance of the interrupt request at the end of the execution of an interrupt processing program to restore the content of the second storage to said stack unit.
摘要翻译：一种数据处理系统，具有用于存储微程序的第一存储器; 地址寄存器，用于提供要执行的微程序的指令地址到所述第一存储器中; 堆叠单元，具有用于在其中存储微程序的返回地址的堆栈区域; 第一控制单元，响应于微指令，用于指示微程序调用将微指令的返回地址存储在堆栈单元中，并且响应于微指令指示从微程序返回以从所述堆栈单元恢复微指令的返回地址; 用于监视中断请求的第二控制单元; 用于在其中保存所述堆叠单元的内容的第二存储器; 状态寄存器，其具有用于在执行微程序的过程中指示接受中断请求的字段;以及第三控制单元，响应于在执行该程序的过程中由第二控制单元检测到中断请求指示状态寄存器接受中断请求的微程序，并将堆栈单元的内容保存在所述第二存储器中，并且响应于在状态寄存器中是否存在指示中断请求的接受，执行中断处理程序以将第二存储器的内容恢复到所述堆栈单元。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式