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    • 10. 发明申请
    • MIS TRANSISTOR AND CMOS TRANSISTOR
    • MIS晶体管和CMOS晶体管
    • US20100038722A1
    • 2010-02-18
    • US12604015
    • 2009-10-22
    • Takefumi NISHIMUTAHiroshi MIYAGITadahiro OHMIShigetoshi SUGAWAAkinobu TERAMOTO
    • Takefumi NISHIMUTAHiroshi MIYAGITadahiro OHMIShigetoshi SUGAWAAkinobu TERAMOTO
    • H01L27/092
    • H01L29/7851H01L21/823807H01L21/823821H01L21/82385H01L29/045
    • A MIS transistor, formed on a semiconductor substrate, assumed to comprise a semiconductor substrate (702, 910) comprising a projecting part (704, 910B) with at least two different crystal planes on the surface on a principal plane, a gate insulator (708, 920B) for covering at least a part of each of said at least two different crystal planes constituting the surface of the projecting part, a gate electrode (706, 930B), comprised on each of said at least two different crystal planes constituting the surface of the projecting part, which sandwiches the gate insulator with the said at least two different planes, and a single conductivity type diffusion region (710a, 710b, 910c, 910d) formed in the projecting part facing each of said at least two different crystal planes and individually formed on both sides of the gate electrode. Such a configuration allows control over increase in the element area and increase of channel width.
    • 形成在半导体衬底上的MIS晶体管被假设为包括半导体衬底(702,910),该半导体衬底包括在主平面上的表面上具有至少两个不同晶面的突出部分(704,910B),栅极绝缘体(708 ,920B),用于覆盖构成所述突出部分的表面的所述至少两个不同晶面的每一个的至少一部分;栅电极(706,930B),包括在构成所述表面的所述至少两个不同晶面中的每一个上 所述突出部分与所述至少两个不同平面夹住所述栅极绝缘体,以及形成在所述突出部分中的所述至少两个不同晶面中的每一个的单导电型扩散区域(710a,710b,910c,910d) 并分别形成在栅电极的两侧。 这种配置允许控制元件面积的增加和通道宽度的增加。