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1. 发明授权

US4523272A Bus selection control in a data transmission apparatus for a multiprocessor system 失效
标题翻译：用于多处理器系统的数据传输装置中的总线选择控制
公开(公告)号：US4523272A
公开(公告)日：1985-06-11
申请号：US366785
申请日：1982-04-08
申请人： Yasushi Fukunaga , Tadaaki Bandoh , Ryosei Hiraoka , Hidekazu Matsumoto , Jushi Ide , Tetsuya Kawakami
发明人： Yasushi Fukunaga , Tadaaki Bandoh , Ryosei Hiraoka , Hidekazu Matsumoto , Jushi Ide , Tetsuya Kawakami
IPC分类号： G06F13/374 , G06F15/16 , G06F15/40
CPC分类号： G06F13/374
摘要： In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.
摘要翻译：在具有主存储器和通过公共地址总线连接的多个处理器，数据总线和用于数据传送的应答总线的多处理器系统中，为每个主存储器和处理器提供数据传输装置，并且包括总线请求控制线，传送总线请求信号和总线控制信号;以及总线控制器，用于响应于总线请求控制线上的信号和请求信号单独控制地址总线，数据总线和应答总线的选择。可以在一个周期内重叠处理，如数据写入和数据写入应答或数据读取和数据读取应答。

2. 发明授权

US4481573A Shared virtual address translation unit for a multiprocessor system 失效
标题翻译：用于多处理器系统的共享虚拟地址转换单元
公开(公告)号：US4481573A
公开(公告)日：1984-11-06
申请号：US320934
申请日：1981-11-13
申请人： Yasushi Fukunaga , Tadaaki Bandoh , Hidekazu Matsumoto , Ryosei Hiraoka , Jushi Ide , Takeshi Kato , Tetsuya Kawakami
发明人： Yasushi Fukunaga , Tadaaki Bandoh , Hidekazu Matsumoto , Ryosei Hiraoka , Jushi Ide , Takeshi Kato , Tetsuya Kawakami
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
CPC分类号： G06F12/1081 , G06F12/0833 , G06F12/1045
摘要： A virtual storage data processing system having an address translation unit shared by a plurality of processors, located in a memory control unit connected to a main memory is disclosed. One of the plurality of processors is a job processor which accesses the main memory with a virtual address to execute an instruction and includes a cache memory which is accessed with a virtual address. One of the plurality of processors is a file processor which accesses the main memory with a virtual address to transfer data between the main memory and an external memory. The cache memory receives the virtual address when the file processor writes to the main memory and if it contains a data block corresponding to the virtual address, it invalidates the corresponding data block. The address translation unit translates the address differently for the access from the file processor and the accesses from other processors.
摘要翻译：公开了一种具有地址转换单元的虚拟存储数据处理系统，该地址转换单元由位于连接到主存储器的存储器控制单元中的多个处理器共享。多个处理器之一是作业处理器，其以虚拟地址访问主存储器以执行指令，并且包括用虚拟地址访问的高速缓冲存储器。多个处理器之一是文件处理器，其以虚拟地址访问主存储器，以在主存储器和外部存储器之间传送数据。当文件处理器写入主存储器时，缓存存储器接收虚拟地址，并且如果其包含与虚拟地址相对应的数据块，则使相应的数据块无效。地址转换单元不同地翻译来自文件处理器的访问以及来自其他处理器的访问。

3. 发明授权

US4530050A Central processing unit for executing instructions of variable length having end information for operand specifiers 失效
标题翻译：用于执行具有操作数说明符的结束信息的可变长度指令的中央处理单元
公开(公告)号：US4530050A
公开(公告)日：1985-07-16
申请号：US408924
申请日：1982-08-17
申请人： Yasushi Fukunaga , Tadaaki Bandoh , Kotaro Hirasawa , Hidekazu Matsumoto , Jushi Ide , Takeshi Katoh , Hiroaki Nakanishi , Tetsuya Kawakami , Ryosei Hiraoka
发明人： Yasushi Fukunaga , Tadaaki Bandoh , Kotaro Hirasawa , Hidekazu Matsumoto , Jushi Ide , Takeshi Katoh , Hiroaki Nakanishi , Tetsuya Kawakami , Ryosei Hiraoka
IPC分类号： G06F9/30 , G06F9/318 , G06F9/36
CPC分类号： G06F9/30167 , G06F9/30152 , G06F9/3016
摘要： A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
摘要翻译：一种用于执行可变长度指令的中央处理单元，其中用于指定操作数的寻址模式的操作数说明符与用于确定操作的种类和操作数的操作码无关。每个操作数说明符由一个或多个数据字节形成，并且具有指示特定操作数说明符是否是最后一个操作数说明符的停止位标志。通过添加停止位标志，可以共享操作数说明符，可以使用相同的操作码执行不同的处理。在操作码解码装置提供指示最后一个操作数的输出的情况下，在对应的操作数说明符中没有检测到停止位平面，相应的指令被检测为错误。

4. 发明授权

US4520441A Data processing system 失效
标题翻译：数据处理系统
公开(公告)号：US4520441A
公开(公告)日：1985-05-28
申请号：US329949
申请日：1981-12-11
申请人： Tadaaki Bandoh , Hidekazu Matsumoto , Yasushi Fukunaga , Ryosei Hiraoka , Jushi Ide , Tetsuya Kawakami
发明人： Tadaaki Bandoh , Hidekazu Matsumoto , Yasushi Fukunaga , Ryosei Hiraoka , Jushi Ide , Tetsuya Kawakami
IPC分类号： G06F12/08 , G06F12/10 , G06F13/00
CPC分类号： G06F12/1027 , G06F12/0866
摘要： A data processing system for supporting a virtual memory is disclosed. Prior to the start of main memory write operation, a processor checks to see if a store buffer has a vacant area to store data to be written into a main memory to execute a current instruction. If a page fault occurs during the main memory write operation, the processor continues to store the subsequent write data for the current instruction and the corresponding virtual or logical addresses in the store buffer to complete execution of the current instruction.
摘要翻译：公开了一种用于支持虚拟存储器的数据处理系统。在主存储器写入操作开始之前，处理器检查存储缓冲器是否具有空闲区域以存储要写入主存储器中的数据以执行当前指令。如果在主存储器写入操作期间发生页错误，则处理器继续存储当前指令的后续写入数据和存储缓冲器中的相应虚拟或逻辑地址，以完成当前指令的执行。

5. 发明授权

US4365311A Control of instruction pipeline in data processing system 失效
标题翻译：控制数据处理系统中的指令流水线
公开(公告)号：US4365311A
公开(公告)日：1982-12-21
申请号：US938346
申请日：1978-08-31
申请人： Yasushi Fukunaga , Tadaaki Bandoh
发明人： Yasushi Fukunaga , Tadaaki Bandoh
IPC分类号： G06F9/30 , G06F9/38 , G06F9/28
CPC分类号： G06F9/3869
摘要： In a data processing system having an instruction pipeline in which each instruction is allotted for execution, part by part, to segments provided in the instruction pipeline so that the first segment executes a part of one instruction allotted thereto, while the successive segments execute respective parts of the preceding instructions allotted thereto, a control of the instruction pipeline is arranged to provide the segments with individual reference clock signals whose timings are determined separately depending on the capacity of each segment for execution of the allotted part of each instruction and also variable depending on the actual condition of the system in execution of each instruction.
摘要翻译：在具有指令流水线的数据处理系统中，其中每个指令被分配用于执行，以逐步地分配到指令流水线中提供的段，使得第一段执行分配给其的一个指令的一部分，而连续的段执行相应的部分指定流水线的控制被布置成为段提供各自的参考时钟信号，其中定时根据用于执行每个指令的分配部分的每个段的容量分别确定，并且还取决于系统执行每条指令的实际情况。

6. 发明授权

US4296468A Address conversion unit for data processing system 失效
标题翻译：数据处理系统地址转换单元
公开(公告)号：US4296468A
公开(公告)日：1981-10-20
申请号：US945396
申请日：1978-09-25
申请人： Tadaaki Bandoh , Yasushi Fukunaga
发明人： Tadaaki Bandoh , Yasushi Fukunaga
IPC分类号： G06F9/34 , G06F12/02 , G06F9/20
CPC分类号： G06F12/0292
摘要： An address conversion method and unit for a data processing system is disclosed which converts logical addresses into physical addresses representative of plural addressable storage locations. Each instruction includes a portion indicative of a first or second kind of instruction. In the case where an instruction is of the first kind, the content of a register in a first base register arrangement specified by the instruction is added with an address part of the instruction to produce a logical address. In the case where an instruction is of the second kind, on the other hand, the content of a register in a second base register arrangement specified by the instruction different from the first base register arrangement is juxtaposed with an address part of the instruction to produce a logical address.
摘要翻译：公开了一种用于数据处理系统的地址转换方法和单元，其将逻辑地址转换为表示多个可寻址存储位置的物理地址。每个指令包括表示第一种或第二类指令的部分。在指令是第一类的情况下，由指令指定的第一基本寄存器装置中的寄存器的内容加上指令的地址部分以产生逻辑地址。另一方面，在指令是第二类的情况下，由与第一基本寄存器装置不同的指令指定的第二基本寄存器装置中的寄存器的内容与指令的地址部分并置，以产生一个逻辑地址。

7. 发明授权

US4523274A Data processing system with processors having different processing speeds sharing a common bus 失效
标题翻译：具有不同处理速度的处理器的数据处理系统共享公共总线
公开(公告)号：US4523274A
公开(公告)日：1985-06-11
申请号：US250644
申请日：1981-04-03
申请人： Yasushi Fukunaga , Tadaaki Bandoh
发明人： Yasushi Fukunaga , Tadaaki Bandoh
IPC分类号： G06F15/16 , G06F1/12 , G06F13/42 , G06F15/177
CPC分类号： G06F13/4217
摘要： There is disclosed a data processing system comprising a plurality of processors having different processing speeds and connected with a synchronous common bus, the processors being able to access a common memory connected with the common bus.A high frequency master clock signal generating means is provided in common for the processors of the system and the respective processors can be operated with the associated different machine cycles determined in accordance with the corresponding different processing speeds by frequency-dividing the master clock signal. In addition, each processor can be operated with different machine cycles depending on its operations.
摘要翻译：公开了一种数据处理系统，包括具有不同处理速度并与同步公共总线连接的多个处理器，处理器能够访问与公共总线连接的公共存储器。为系统的处理器共同提供高频主时钟信号发生装置，并且可以通过对主时钟信号进行分频，根据相应的不同处理速度确定相关的不同机器周期来操作相应的处理器。此外，每个处理器可以根据其操作以不同的机器周期进行操作。

8. 发明授权

US06385339B1 Collaborative learning system and pattern recognition method 失效
标题翻译：协同学习系统和模式识别方法
公开(公告)号：US06385339B1
公开(公告)日：2002-05-07
申请号：US09609326
申请日：2000-06-30
申请人： Toshimi Yokota , Hiroshi Shojima , Soshiro Kuzunuki , Toshifumi Arai , Masaki Miura , Keiko Gunji , Yasushi Fukunaga
发明人： Toshimi Yokota , Hiroshi Shojima , Soshiro Kuzunuki , Toshifumi Arai , Masaki Miura , Keiko Gunji , Yasushi Fukunaga
IPC分类号： G06K900
CPC分类号： G06K9/6255 , G06K9/6807
摘要： The present invention relates to a multi-user pattern data processing system configured for various kinds of patterns, such as characters, to learn efficiently and effectively. The present invention comprises an input arrangement 1 having patterns entered therein from a plurality of users, a dictionary 2 having patterns and attributes of the patterns belonging thereto defined therein, a recognizing arrangement 4 that receives the entered pattern and a group attribute and retrieves from among the patterns entered in the dictionary and having a corresponding group attribute to feed out the category, and a dictionary editing arrangement 5 for extracting a pattern used in common by a group before editing the pattern, such as entering it in the common dictionary, with the group having the user made to belong thereto. The invention allows the dictionary used to the pattern recognition to learn very efficiently and effectively.
摘要翻译：本发明涉及一种多用户模式数据处理系统，其被配置用于诸如角色的各种模式，以有效且高效地学习。本发明包括具有从多个用户输入的图案的输入装置1，具有其中定义的图案和属性的图案和属性的字典2，接收输入的图案的识别装置4和组属性，并从其中检索在字典中输入的具有对应的组属性以输出类别的图案，以及字典编辑装置5，用于在编辑图案之前提取组中共同使用的图案，例如将其输入公共字典，具有使用者属于其的组。本发明允许用于模式识别的字典非常有效和高效地学习。

9. 发明授权

US5900917A Image composing and displaying method and apparatus 失效
标题翻译：图像构成及显示方法及装置
公开(公告)号：US5900917A
公开(公告)日：1999-05-04
申请号：US903259
申请日：1997-07-25
申请人： Norifumi Yanai , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga
发明人： Norifumi Yanai , Ryo Fujita , Koyo Katsura , Yasushi Fukunaga
IPC分类号： G06T1/20 , G09G5/36 , G09G5/39 , G09G5/399 , H04N5/262 , H04N7/26 , H04N7/50 , H04N5/445
CPC分类号： G09G5/39 , G06T1/20 , H04N19/42 , H04N19/61 , H04N5/2624 , G09G2340/125 , G09G2360/123 , G09G5/36 , G09G5/399
摘要： An image composing and displaying apparatus includes frame memory constituent elements of an identical structure, a video input section, a video output section, a controller for selecting connection of each element to the video input or output section, and an image drawing section for reading and writing video data from and in the elements. The memory elements can be used for the input and output operations and hence the size thereof can be easily expanded; moreover the numbers of the elements respectively connected to the video input and output sections can be adaptively varied.
摘要翻译：图像合成显示装置包括具有相同结构的帧存储器组成元件，视频输入部分，视频输出部分，用于选择每个元素与视频输入或输出部分的连接的控制器，以及用于读取和从元素中写入视频数据。存储元件可用于输入和输出操作，因此其尺寸可以容易地扩展; 此外，分别连接到视频输入和输出部分的元件的数量可以自适应地变化。

10. 发明授权

US5841901A Pattern recognition system 失效
标题翻译：模式识别系统
公开(公告)号：US5841901A
公开(公告)日：1998-11-24
申请号：US460599
申请日：1995-06-02
申请人： Toshifumi Arai , Hiroshi Shojima , Masaki Miura , Yasushi Fukunaga
发明人： Toshifumi Arai , Hiroshi Shojima , Masaki Miura , Yasushi Fukunaga
IPC分类号： G06K9/03 , G06K9/62 , G06K9/66 , G06K9/68 , G06K9/70
CPC分类号： G06K9/6255 , G06K9/6292
摘要： A pattern recognition system having a plurality of dictionaries, wherein handwritten input information is compared with patterns contained in the plurality of dictionaries so as to deliver a similar one of the patterns as a recognized result; The system comprises a controller which selects one pattern as a final recognized result from among recognized results based on the plurality of dictionaries, so as to deliver the selected pattern as its output. The controller evaluates summations of values previously set for respective candidate levels in the recognized results, for individual candidate patterns which exist in the recognized results based on the plurality of dictionaries, and it selects the pattern of the final recognized result on the basis of the summations. Thus, the recognized result most suited to a user is automatically derived from among the recognized results based on the plurality of dictionaries.
摘要翻译：一种具有多个词典的模式识别系统，其中手写输入信息与包含在多个词典中的图案进行比较，以便将相似的一个模式作为识别结果; 该系统包括控制器，其基于多个字典从识别的结果中选择一个模式作为最终识别结果，以便将所选择的模式作为其输出。控制器基于多个词典评估先前为识别结果中为各候选等级设置的值的总和，对于基于多个词典的识别结果中存在的各个候选模式，并且基于求和来选择最终识别结果的模式。因此，最适合于用户的识别结果是自动地从基于多个字典的识别结果中导出的。

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