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1. 发明申请

US20120181653A1 SEMICONDUCTOR PN JUNCTION STRUCTURE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体PN结结构及其制造方法
公开(公告)号：US20120181653A1
公开(公告)日：2012-07-19
申请号：US13005754
申请日：2011-01-13
申请人： TSUNG-YI HUANG , Hung-Der Su , Kuo-Cheng Chang , Chun-Yi Hung , Kuo-Hsuan Lo , Jeng Gong
发明人： TSUNG-YI HUANG , Hung-Der Su , Kuo-Cheng Chang , Chun-Yi Hung , Kuo-Hsuan Lo , Jeng Gong
IPC分类号： H01L29/06 , H01L21/04
CPC分类号： H01L29/0688 , H01L29/0634 , H01L29/0692
摘要： The present invention discloses a semiconductor PN junction structure and a manufacturing method thereof. From top view, the PN junction includes a staggered comb-teeth structure. The PN junction forms a depletion region with enhanced breakdown voltage, hence broadening the applications of a semiconductor device having such PN junction.
摘要翻译：本发明公开了一种半导体PN结结构及其制造方法。从顶视图，PN结包括交错的梳齿结构。 PN结形成具有增强的击穿电压的耗尽区，因此拓宽了具有这种PN结的半导体器件的应用。

2. 发明申请

US20120223384A1 HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：高压器件及其制造方法
公开(公告)号：US20120223384A1
公开(公告)日：2012-09-06
申请号：US13037678
申请日：2011-03-01
申请人： TSUNG-YI HUANG , Kuo-Hsuan Lo
发明人： TSUNG-YI HUANG , Kuo-Hsuan Lo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66681 , H01L29/0619 , H01L29/0634 , H01L29/0653 , H01L29/0847 , H01L29/1045 , H01L29/42368 , H01L29/7835
摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a first conductive type substrate in which isolation regions are formed for defining a device region; a gate formed on the first conductive type substrate; a source and a drain formed in the device region and located at both sides of the gate respectively, and doped with second conductive type impurities; a second conductive type well, which is formed in the first conductive type substrate, and surrounds the drain from top view; and a first deep trench isolation structure, which is formed in the first conductive type substrate, and is located in the second conductive type well between the source and the drain from top view, wherein the depth of the first deep trench isolation structure is deeper than the second conductive type well from the cross-sectional view.
摘要翻译：本发明公开了一种高压器件及其制造方法。高压器件包括：第一导电型衬底，其中形成隔离区以限定器件区域; 形成在所述第一导电型基板上的栅极; 在器件区域中分别形成并位于栅极两侧的源极和漏极，并掺杂有第二导电类型杂质; 第二导电型阱，其形成在第一导电类型基板中，并且从俯视图围绕漏极; 以及第一深沟槽隔离结构，其形成在第一导电类型基板中，并且从顶视图位于源极和漏极之间的第二导电类型阱中，其中第一深沟槽隔离结构的深度比第二导电类型井从横截面图。

3. 发明申请

US20120267767A1 SEMICONDUCTOR OVERLAPPED PN STRUCTURE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体超导PN结构及其制造方法
公开(公告)号：US20120267767A1
公开(公告)日：2012-10-25
申请号：US13090449
申请日：2011-04-20
申请人： TSUNG-YI HUANG , Chien-Hao Huang , Ying-Shiou Lin
发明人： TSUNG-YI HUANG , Chien-Hao Huang , Ying-Shiou Lin
IPC分类号： H01L29/02 , H01L21/265
CPC分类号： H01L29/06 , H01L21/266 , H01L29/0688 , H01L29/36
摘要： The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.
摘要翻译：本发明公开了半导体重叠PN结构及其制造方法。该方法包括：提供衬底; 提供第一掩模以限定所述衬底中的P（或N）型阱和至少一个重叠区域; 将P（或N）型杂质注入P（或N）型阱和至少一个重叠区域; 提供具有至少一个开口的第二掩模，以在所述衬底中限定N（或P）型阱，并且在所述至少一个重叠区域中限定至少一个双注入区域; 将N（或P）型杂质注入N（或P）型阱和至少一个双注入区，使得至少一个双注入区具有P型和N型杂质。

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