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1. 发明申请

US20140175520A1 METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME 有权
标题翻译：金属硅化物自对准SiGe异相双极晶体管及其形成方法
公开(公告)号：US20140175520A1
公开(公告)日：2014-06-26
申请号：US14189106
申请日：2014-02-25
申请人： Tsinghua University
发明人： Jun Fu , Yu-dong Wang , Wei Zhang , Gao-qing Li , Zheng-li Wu , Jie Cui , Yue Zhao , Zhi-hong Liu
IPC分类号： H01L29/737 , H01L29/66
CPC分类号： H01L29/7378 , H01L29/66242 , H01L29/66318
摘要： The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance RB of the prior art products. The metal silicide self-aligned SiGe heterojunction bipolar transistor of the present invention mainly comprises an Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region composed of a liner silicon oxide layer and a silicon nitride inner sidewall, a monocrystalline emitter region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode. The base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region. The present invention discloses a method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is used to form the aforesaid bipolar transistor. The metal silicide self-aligned SiGe heterojunction bipolar transistor and the method of forming the same of the present invention can reduce the base resistance RB, and feature a simple process and a low cost.
摘要翻译：本发明公开了一种金属硅化物自对准SiGe异质结双极晶体管，其被设计为克服现有技术产品的大的基极电阻RB等缺点。本发明的金属硅化物自对准SiGe异质结双极晶体管主要包括Si集电极区域，局部电介质区域，基极区域，基极区域低电阻金属硅化物层，多晶硅发射极区域，发射极基极由衬垫氧化硅层和氮化硅内侧壁，单晶发射区，接触孔电介质层，发射极金属电极和贱金属电极组成的间隔电介质区。基极区低电阻金属硅化物层一直延伸到发射极 - 基极间隔电介质区域的外部。本发明公开了一种用于形成上述双极晶体管的金属硅化物自对准SiGe异质结双极晶体管的形成方法。金属硅化物自对准SiGe异质结双极晶体管及其形成本发明的方法可以降低基极电阻RB，并且具有简单的工艺和低成本。

2. 发明授权

US09202901B2 Metal silicide self-aligned SiGe heterojunction bipolar transistor and method of forming the same 有权
标题翻译：金属硅化物自对准SiGe异质结双极晶体管及其形成方法
公开(公告)号：US09202901B2
公开(公告)日：2015-12-01
申请号：US14189106
申请日：2014-02-25
申请人： Tsinghua University
发明人： Jun Fu , Yu-dong Wang , Wei Zhang , Gao-qing Li , Zheng-li Wu , Jie Cui , Yue Zhao , Zhi-hong Liu
IPC分类号： H01L29/737 , H01L29/66 , H01L29/73 , H01L29/165 , H01L21/265
CPC分类号： H01L29/7378 , H01L29/66242 , H01L29/66318
摘要： The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance RB of the prior art products. The metal silicide self-aligned SiGe heterojunction bipolar transistor of the present invention mainly comprises an Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region composed of a liner silicon oxide layer and a silicon nitride inner sidewall, a monocrystalline emitter region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode. The base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region. The present invention discloses a method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is used to form the aforesaid bipolar transistor. The metal silicide self-aligned SiGe heterojunction bipolar transistor and the method of forming the same of the present invention can reduce the base resistance RB, and feature a simple process and a low cost.
摘要翻译：本发明公开了一种金属硅化物自对准SiGe异质结双极晶体管，其被设计为克服现有技术产品的大的基极电阻RB等缺点。本发明的金属硅化物自对准SiGe异质结双极晶体管主要包括Si集电极区域，局部电介质区域，基极区域，基极区域低电阻金属硅化物层，多晶硅发射极区域，发射极基极由衬垫氧化硅层和氮化硅内侧壁，单晶发射区，接触孔电介质层，发射极金属电极和贱金属电极组成的间隔电介质区。基极区低电阻金属硅化物层一直延伸到发射极 - 基极间隔电介质区域的外部。本发明公开了一种用于形成上述双极晶体管的金属硅化物自对准SiGe异质结双极晶体管的形成方法。金属硅化物自对准SiGe异质结双极晶体管及其形成本发明的方法可以降低基极电阻RB，并且具有简单的工艺和低成本。

3. 发明申请

US20140329368A1 BIPOLAR TRANSISTOR WITH EMBEDDED EPITAXIAL EXTERNAL BASE REGION AND METHOD OF FORMING THE SAME 有权
标题翻译：具有嵌入式外延基底区域的双极晶体管及其形成方法
公开(公告)号：US20140329368A1
公开(公告)日：2014-11-06
申请号：US14335468
申请日：2014-07-18
申请人： TSINGHUA UNIVERSITY
发明人： Yu-dong Wang , Jun Fu , Jie Cui , Yue Zhao , Zhi-hong Liu , Wei Zhang , Gao-qing Li , Zheng-li Wu , Ping Xu
IPC分类号： H01L29/66
CPC分类号： H01L29/66234 , H01L29/0817 , H01L29/1004 , H01L29/165 , H01L29/207 , H01L29/66242 , H01L29/7378
摘要： The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region. The bipolar transistor with an embedded epitaxial external base region of the present invention avoids the TED effect and reduces the resistance of the external base region of the device so that the performance of the device is improved. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance.
摘要翻译：本发明公开了一种具有嵌入式外延外部基极区域的双极晶体管，其被设计用于解决现有技术结构的TED效应的问题。具有本发明的嵌入式外延外部基极区域的双极晶体管至少包括集电极区域，基极区域和集电极区域上的外部基极区域，基极区域上的发射极和发射极两侧的侧壁。外部基极区域通过原位掺杂选择性外延工艺生长并嵌入集电极区域。外部基部区域的一部分位于侧壁下方。本发明公开了一种形成具有嵌入式外延基极区域的双极晶体管的方法。具有本发明的嵌入式外延外部基极区域的双极晶体管避免了TED效应，并且降低了器件的外部基极区域的电阻，从而提高了器件的性能。本发明的具有嵌入式外延外部基极区域的双极晶体管的形成方法实现了具有嵌入式外延基极区域的上述双极晶体管，其特征是简洁的步骤，成本低，操作简单，所获得的结构具有良好的性能。

4. 发明申请

US20130313614A1 METAL SILICIDE SELF-ALIGNED SiGe HETEROJUNCTION BIPOLAR TRANSISTOR AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：金属硅化物自对准SiGe异相双极晶体管及其形成方法
公开(公告)号：US20130313614A1
公开(公告)日：2013-11-28
申请号：US13625233
申请日：2012-09-24
申请人： TSINGHUA UNIVERSITY
发明人： Jun Fu , Yu-dong Wang , Wei Zhang , Gao-qing Li , Zheng-li Wu , Jie Cui , Yue Zhao , Zhi-hong Liu
IPC分类号： H01L21/331 , H01L29/737
CPC分类号： H01L29/7378 , H01L29/66242 , H01L29/66318
摘要： The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance RB of the prior art products. The metal silicide self-aligned SiGe heterojunction bipolar transistor of the present invention mainly comprises an Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region composed of a liner silicon oxide layer and a silicon nitride inner sidewall, a monocrystalline emitter region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode. The base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region. The present invention discloses a method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is used to form the aforesaid bipolar transistor. The metal silicide self-aligned SiGe heterojunction bipolar transistor and the method of forming the same of the present invention can reduce the base resistance RB, and feature a simple process and a low cost.
摘要翻译：本发明公开了一种金属硅化物自对准SiGe异质结双极晶体管，其被设计为克服现有技术产品的大的基极电阻RB等缺点。本发明的金属硅化物自对准SiGe异质结双极晶体管主要包括Si集电极区域，局部电介质区域，基极区域，基极区域低电阻金属硅化物层，多晶硅发射极区域，发射极基极由衬垫氧化硅层和氮化硅内侧壁，单晶发射区，接触孔电介质层，发射极金属电极和贱金属电极组成的间隔电介质区。基极区低电阻金属硅化物层一直延伸到发射极 - 基极间隔电介质区域的外部。本发明公开了一种用于形成上述双极晶体管的金属硅化物自对准SiGe异质结双极晶体管的形成方法。金属硅化物自对准SiGe异质结双极晶体管及其形成本发明的方法可以降低基极电阻RB，并且具有简单的工艺和低成本。

5. 发明申请

US20130307122A1 BIPOLAR TRANSISTOR WITH EMBEDDED EPITAXIAL EXTERNAL BASE REGION AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：具有嵌入式外延基底区域的双极晶体管及其形成方法
公开(公告)号：US20130307122A1
公开(公告)日：2013-11-21
申请号：US13625211
申请日：2012-09-24
申请人： TSINGHUA UNIVERSITY
发明人： Yu-dong Wang , Jun Fu , Jie Cui , Yue Zhao , Zhi-hong Liu , Wei Zhang , Gao-qing Li , Zheng-li Wu , Ping Xu
IPC分类号： H01L29/73 , H01L21/331
CPC分类号： H01L29/66234 , H01L29/0817 , H01L29/1004 , H01L29/165 , H01L29/207 , H01L29/66242 , H01L29/7378
摘要： The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region. The bipolar transistor with an embedded epitaxial external base region of the present invention avoids the TED effect and reduces the resistance of the external base region of the device so that the performance of the device is improved. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance.
摘要翻译：本发明公开了一种具有嵌入式外延外部基极区域的双极晶体管，其被设计用于解决现有技术结构的TED效应的问题。具有本发明的嵌入式外延外部基极区域的双极晶体管至少包括集电极区域，基极区域和集电极区域上的外部基极区域，基极区域上的发射极和发射极两侧的侧壁。外部基极区域通过原位掺杂选择性外延工艺生长并嵌入集电极区域。外部基部区域的一部分位于侧壁下方。本发明公开了一种形成具有嵌入式外延基极区域的双极晶体管的方法。具有本发明的嵌入式外延外部基极区域的双极晶体管避免了TED效应，并且降低了器件的外部基极区域的电阻，从而提高了器件的性能。本发明的具有嵌入式外延外部基极区域的双极晶体管的形成方法实现了具有嵌入式外延基极区域的上述双极晶体管，其特征是简洁的步骤，成本低，操作简单，所获得的结构具有良好的性能。

6. 发明授权

US09922888B2 General four-port on-wafer high frequency de-embedding method 有权
公开(公告)号：US09922888B2
公开(公告)日：2018-03-20
申请号：US15143921
申请日：2016-05-02
申请人： Tsinghua University
发明人： Jun Fu , Yu-dong Wang , Jie Cui , Yue Zhao , Wen-pu Cui , Zhi-hong Liu
IPC分类号： G01R31/26 , H01L21/66 , G01R27/28 , G01R27/26 , G01R27/02
CPC分类号： H01L22/14 , G01R27/02 , G01R27/2623 , G01R27/28 , H01L22/32 , H01L22/34
摘要： The present invention provides a general four-port on-wafer high frequency de-embedding method. The method comprises: for each on-wafer de-embedding dummy, building a model considering the distributive nature of high frequency characteristics of the on-wafer de-embedding dummy; obtaining the intrinsic Y-parameter admittance matrix of said N on-wafer de-embedding dummies by calculation or simulation by using said models; and solving the equation set which the corresponding measurement and calculation or simulation data of said on-wafer de-embedding dummies satisfy for the elements of the related admittance matrices of the parasitic four-port network to be stripped in de-embedding and model parameters of models on which said calculation or simulation is based.

7. 发明授权

US09012291B2 Bipolar transistor with embedded epitaxial external base region and method of forming the same 有权
标题翻译：具有嵌入式外延基极区域的双极晶体管及其形成方法
公开(公告)号：US09012291B2
公开(公告)日：2015-04-21
申请号：US14335468
申请日：2014-07-18
申请人： Tsinghua University
发明人： Yu-dong Wang , Jun Fu , Jie Cui , Yue Zhao , Zhi-hong Liu , Wei Zhang , Gao-qing Li , Zheng-li Wu , Ping Xu
IPC分类号： H01L21/331 , H01L21/02 , H01L29/66 , H01L29/737 , H01L29/02 , H01L29/10 , H01L29/08 , H01L29/165 , H01L29/207
CPC分类号： H01L29/66234 , H01L29/0817 , H01L29/1004 , H01L29/165 , H01L29/207 , H01L29/66242 , H01L29/7378
摘要： The present invention discloses a bipolar transistor with an embedded epitaxial external base region, which is designed to solve the problem of the TED effect with the prior art structures. The bipolar transistor with an embedded epitaxial external base region of the present invention comprises at least a collector region, a base region and an external base region on the collector region, an emitter on the base region, and sidewalls at both sides of the emitter. The external base region is grown through an in-situ doping selective epitaxy process and is embedded in the collector region. A portion of the external base region is located beneath the sidewalls. The present invention discloses a method of forming a bipolar transistor with an embedded epitaxial external base region. The bipolar transistor with an embedded epitaxial external base region of the present invention avoids the TED effect and reduces the resistance of the external base region of the device so that the performance of the device is improved. The method of forming a bipolar transistor with an embedded epitaxial external base region of the present invention achieves the aforesaid bipolar transistor with an embedded epitaxial external base region, and features concise steps, a low cost and simple operations, and the structure obtained has good performance.
摘要翻译：本发明公开了一种具有嵌入式外延外部基极区域的双极晶体管，其被设计用于解决现有技术结构的TED效应的问题。具有本发明的嵌入式外延外部基极区域的双极晶体管至少包括集电极区域，基极区域和集电极区域上的外部基极区域，基极区域上的发射极和发射极两侧的侧壁。外部基极区域通过原位掺杂选择性外延工艺生长并嵌入集电极区域。外部基部区域的一部分位于侧壁下方。本发明公开了一种形成具有嵌入式外延基极区域的双极晶体管的方法。具有本发明的嵌入式外延外部基极区域的双极晶体管避免了TED效应，并且降低了器件的外部基极区域的电阻，从而提高了器件的性能。本发明的具有嵌入式外延外部基极区域的双极晶体管的形成方法实现了具有嵌入式外延基极区域的上述双极晶体管，其特征是简洁的步骤，成本低，操作简单，所获得的结构具有良好的性能。

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