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    • 3. 发明授权
    • Insulated gate switching element
    • 绝缘栅开关元件
    • US09525062B2
    • 2016-12-20
    • US15133993
    • 2016-04-20
    • Toyota Jidosha Kabushiki Kaisha
    • Takashi IshidaTakashi Okawa
    • H01L21/00H01L29/78H01L29/06H01L29/10
    • H01L29/7824H01L29/0634H01L29/1083H01L29/1095H01L29/78H01L29/7823
    • An insulated gate switching element includes: a semiconductor substrate; a gate insulating film disposed on a surface of the semiconductor substrate; and a gate electrode disposed on the gate insulating film. The semiconductor substrate includes a first semiconductor region, a base region, and a second semiconductor region. The gate electrode faces the base region with the gate insulating film interposed therebetween. A high-resistance region, which is separated from the gate insulating film and has higher resistance to a number of carriers of a first conduction type semiconductor than that of the base region, is disposed in at least one of a first interface which is an interface between the base region and the first semiconductor region and a second interface which is an interface between the base region and the second semiconductor region.
    • 绝缘栅极开关元件包括:半导体衬底; 设置在所述半导体基板的表面上的栅极绝缘膜; 以及设置在栅极绝缘膜上的栅电极。 半导体衬底包括第一半导体区域,基极区域和第二半导体区域。 栅极电极面对基极区域,栅绝缘膜插入其间。 与第一导电型半导体的载流子相比,与栅极绝缘膜分离并且对第一导电型半导体的载流子的耐受性高于基极区域的高电阻区域设置在作为界面的第一界面中的至少一个 在所述基极区域和所述第一半导体区域之间,以及作为所述基极区域和所述第二半导体区域之间的界面的第二界面。
    • 4. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20160240635A1
    • 2016-08-18
    • US15044167
    • 2016-02-16
    • Toyota Jidosha Kabushiki Kaisha
    • Takashi Okawa
    • H01L29/735H01L29/10H01L29/08
    • H01L29/735H01L29/0603H01L29/0615H01L29/1008H01L29/7317
    • A semiconductor device includes a first main electrode; a second main electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of the first conductivity type; a third semiconductor region of a second conductivity type arranged between the first semiconductor region and the second semiconductor region; and a depletion layer suppression region arranged inside of the third semiconductor region and being configured to suppress a spread of a depletion layer extending in the third semiconductor region when a reverse bias voltage is applied between the second semiconductor region and the third semiconductor region. The third semiconductor region includes a shortest region where a distance between a first boundary surface and a second boundary surface is shortest, and the shortest region includes a region where the depletion layer suppression region does not exist between the first boundary surface and the second boundary surface.
    • 半导体器件包括第一主电极; 第二主电极; 第一导电类型的第一半导体区域; 第一导电类型的第二半导体区域; 布置在第一半导体区域和第二半导体区域之间的第二导电类型的第三半导体区域; 以及耗尽层抑制区域,其设置在第三半导体区域的内部,并且被配置为当在第二半导体区域和第三半导体区域之间施加反向偏置电压时,抑制在第三半导体区域中延伸的耗尽层的扩展。 第三半导体区域包括第一边界面和第二边界面之间的距离最短的最短区域,最短区域包括在第一边界面和第二边界面之间不存在耗尽层抑制区域的区域 。