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1. 发明申请

US20190245086A1 Stressing Structure With Low Hydrogen Content Layer Over NiSi Salicide 审中-公开
公开(公告)号：US20190245086A1
公开(公告)日：2019-08-08
申请号：US15888071
申请日：2018-02-04
申请人： Tower Semiconductor Ltd.
发明人： Alexey Heiman , Igor Aisenberg , Abed Qaddah , Yakov Roizin
IPC分类号： H01L29/78 , H01L29/45 , H01L21/02 , H01L21/285 , H01L21/28
摘要： A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.

2. 发明授权

US10788375B2 Apparatus, system and method of a temperature sensor 有权
公开(公告)号：US10788375B2
公开(公告)日：2020-09-29
申请号：US15834505
申请日：2017-12-07
申请人： TOWER SEMICONDUCTOR LTD.
发明人： Yakov Roizin , Menachem Vofsy , Alexey Heiman , Yossi Rosenwaks , Klimentiy Shimanovich , Yhonatan Vaknin
IPC分类号： G01K7/01 , H01L29/16 , G01N33/00 , H01L23/34 , G01K7/00 , G01K7/16 , H01L29/06 , H01L29/40 , H01L29/775
摘要： Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.

3. 发明授权

US10770573B2 Apparatus, system and method of an electrostatically formed nanowire (EFN) 有权
公开(公告)号：US10770573B2
公开(公告)日：2020-09-08
申请号：US16136714
申请日：2018-09-20
申请人： TOWER SEMICONDUCTOR LTD. , RAMOT at Tel Aviv University Ltd.
发明人： Zohar Shaked , Yakov Roizin , Menachem Vofsy , Alexey Heiman , Yossi Rosenwaks , Klimentiy Shimanovich , Yhonatan Vaknin
IPC分类号： H01L29/775 , G01N27/414 , H01L29/10 , H01L27/12 , H01L29/66 , H01L29/423
摘要： For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

4. 发明授权

US10770586B2 Stressing structure with low hydrogen content layer over NiSi salicide 有权
公开(公告)号：US10770586B2
公开(公告)日：2020-09-08
申请号：US15888071
申请日：2018-02-04
申请人： Tower Semiconductor Ltd.
发明人： Alexey Heiman , Igor Aisenberg , Abed Qaddah , Yakov Roizin
IPC分类号： H01L29/78 , H01L29/45 , H01L21/28 , H01L21/02 , H01L21/285
摘要： A multi-layer SiN stressing stack (structure) including a thin lower SiN layer and a thick upper SiN layer is formed over NiSi silicide structures and functions to generate tensile channel stress in NMOS transistors. The lower SiN layer is formed directly on the silicided surfaces, and has a low hydrogen content and a relatively low residual stress. The upper SiN layer is then formed on the lower SiN layer using process parameters that produce a relatively high residual stress, and also cause the upper SiN material to have relatively high hydrogen content. The lower SiN layer functions as a barrier that prevents/minimizes hydrogen migration to the silicide structures, which prevents defects leading to NiSi failures. The upper SiN layer functions to generate desirable high tensile stress in the underlying NMOS channel region to enhance the mobility of channel electrons. In some embodiments other dielectric materials are used.

5. 发明申请

US20170018503A1 SEMICONDUCTOR DIE WITH A METAL VIA 有权
标题翻译： SEMICONDUCTOR DIE WITH METAL VIA
公开(公告)号：US20170018503A1
公开(公告)日：2017-01-19
申请号：US14798535
申请日：2015-07-14
申请人： Tower Semiconductor Ltd.
发明人： Sharon Levin , Alexey Heiman , Sagy Levy
IPC分类号： H01L23/528 , H01L29/78 , H01L27/092
CPC分类号： H01L27/092 , H01L21/743 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/1083 , H01L29/1087 , H01L29/7816
摘要： A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor, extends between the metal layer and the substrate, and penetrates the substrate.
摘要翻译：可以包括基板的半导体管芯; 外延层; 金属层; 第一晶体管; 并且围绕第一晶体管的金属通孔在金属层和基板之间延伸并且穿透基板。

6. 发明申请

US20200273972A1 APPARATUS, SYSTEM AND METHOD OF AN ELECTROSTATICALLY FORMED NANOWIRE (EFN) 审中-公开
公开(公告)号：US20200273972A1
公开(公告)日：2020-08-27
申请号：US16870980
申请日：2020-05-10
申请人： TOWER SEMICONDUCTOR LTD. , RAMOT at Tel Aviv University Ltd.
发明人： Zohar Shaked , Yakov Roizin , Menachem Vofsy , Alexey Heiman , Yossi Rosenwaks , Klimentiy Shimanovich , Yhonatan Vaknin
IPC分类号： H01L29/775 , G01N27/414 , H01L29/10 , H01L27/12 , H01L29/66 , H01L29/423
摘要： For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

7. 发明申请

US20200098906A1 APPARATUS, SYSTEM AND METHOD OF AN ELECTROSTATICALLY FORMED NANOWIRE (EFN) 审中-公开
公开(公告)号：US20200098906A1
公开(公告)日：2020-03-26
申请号：US16136714
申请日：2018-09-20
申请人： TOWER SEMICONDUCTOR LTD. , RAMOT at Tel Aviv University Ltd.
发明人： Zohar Shaked , Yakov Roizin , Menachem Vofsy , Alexey Heiman , Yossi Rosenwaks , Klimentiy Shimanovich , Yhonatan Vaknin
IPC分类号： H01L29/775 , G01N27/414 , H01L29/10 , H01L29/423 , H01L27/12 , H01L29/66
摘要： For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

8. 发明授权

US09837411B2 Semiconductor die with a metal via 有权
公开(公告)号：US09837411B2
公开(公告)日：2017-12-05
申请号：US14798535
申请日：2015-07-14
申请人： Tower Semiconductor Ltd.
发明人： Sharon Levin , Alexey Heiman , Sagy Levy
IPC分类号： H01L21/70 , H01L27/092 , H01L21/74 , H01L29/78 , H01L29/10
CPC分类号： H01L27/092 , H01L21/743 , H01L21/823814 , H01L21/823892 , H01L27/0922 , H01L29/1083 , H01L29/1087 , H01L29/7816
摘要： A semiconductor die that may include a substrate; an epitaxial layer; a metal layer; a first transistor; and a metal via that surrounds the first transistor, extends between the metal layer and the substrate, and penetrates the substrate.

9. 发明授权

US08722496B1 Method for making embedded cost-efficient SONOS non-volatile memory 有权
标题翻译：嵌入式经济高效SONOS非易失性存储器的方法
公开(公告)号：US08722496B1
公开(公告)日：2014-05-13
申请号：US13756497
申请日：2013-01-31
申请人： Tower Semiconductor Ltd.
发明人： Yakov Roizin , Evgeny Pikhay , Alexey Heiman , Micha Gutman
IPC分类号： H01L21/336
CPC分类号： H01L29/66833 , H01L21/28282 , H01L27/11573 , H01L29/792
摘要： A cost-efficient SONOS (CEONOS) non-volatile memory (NVM) cell production method for CMOS ICs, where the CEONOS NVM cell requires two or three additional masks, but can otherwise be formed using the same standard CMOS flow processes used to form NMOS transistors. A first additional mask is used to form an oxide-nitride-oxide (ONO) layer that replaces the standard NMOS gate oxide and serves to store NVM data (i.e., trapped charges). A second additional mask is used to perform drain engineering, including a special pocket implant and LDD extensions, which facilitates program/erase of the CEONOS NVM cells using low voltages (e.g., 5V). The polysilicon gate, source/drain contacts and metallization are formed using corresponding NMOS processes. The CEONOS NVM cells are arranged in a space-efficient X-array pattern such that each group of four cells share three bit lines. Programming involves standard CHE injection or pulse agitated interface substrate hot electron injection (PAISHEI).
摘要翻译：用于CMOS IC的具有成本效益的SONOS（CEONOS）非易失性存储器（NVM）电池制造方法，其中CEONOS NVM单元需要两个或三个附加掩模，但是否则可以使用用于形成NMOS的相同的标准CMOS流程形成晶体管。使用第一附加掩模来形成替代标准NMOS栅极氧化物并用于存储NVM数据（即，捕获的电荷）的氧化物 - 氮化物 - 氧化物（ONO）层。第二个附加掩模用于执行漏极工程，包括特殊的口袋注入和LDD扩展，这有助于使用低电压（例如5V）对CEONOS NVM单元进行编程/擦除。使用相应的NMOS工艺形成多晶硅栅极，源极/漏极接触和金属化。 CEONOS NVM单元以空间有效的X阵列模式排列，使得每组四个单元共享三个位线。编程涉及标准CHE注入或脉冲搅拌界面基板热电子注入（PAISHEI）。

10. 发明授权

US11374120B2 Apparatus, system and method of an electrostatically formed nanowire (EFN) 有权
公开(公告)号：US11374120B2
公开(公告)日：2022-06-28
申请号：US16870980
申请日：2020-05-10
申请人： TOWER SEMICONDUCTOR LTD. , RAMOT at Tel Aviv University Ltd.
发明人： Zohar Shaked , Yakov Roizin , Menachem Vofsy , Alexey Heiman , Yossi Rosenwaks , Klimentiy Shimanovich , Yhonatan Vaknin
IPC分类号： H01L29/775 , G01N27/414 , H01L29/10 , H01L27/12 , H01L29/66 , H01L29/423
摘要： For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

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