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1. 发明申请

US20170109054A1 NONVOLATILE LOGIC MEMORY FOR COMPUTING MODULE RECONFIGURATION 审中-公开
公开(公告)号：US20170109054A1
公开(公告)日：2017-04-20
申请号：US14887885
申请日：2015-10-20
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F3/06 , G06F13/28 , G06F13/42 , H04L29/08
CPC分类号： G06F13/4234 , G06F13/28 , H04L67/303
摘要： Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

2. 发明授权

US09454437B2 Non-volatile logic based processing device 有权
标题翻译：基于非易失性逻辑的处理器件
公开(公告)号：US09454437B2
公开(公告)日：2016-09-27
申请号：US14309362
申请日：2014-06-19
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F11/00 , G06F11/14 , G06F9/44
CPC分类号： G06F11/1417 , G06F9/4401 , G06F9/4418 , G06F11/1469
摘要： A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
摘要翻译：处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。标准引导顺序用于恢复数据的第一部分。数据的第二部分与标准引导序列并行地从NVL阵列恢复。对数据的第二部分执行数据损坏检查。如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。

3. 发明申请

US20150089293A1 Non-Volatile Logic Based Processing Device 有权
标题翻译：基于非易失性逻辑的处理器件
公开(公告)号：US20150089293A1
公开(公告)日：2015-03-26
申请号：US14309362
申请日：2014-06-19
申请人： TEXAS INSTRUMENTS INCORPORATED , TEXAS INSTRUMENTS DEUTSCHLAND GMBH
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F11/14 , G06F9/44 , G06F12/02
CPC分类号： G06F11/1417 , G06F9/4401 , G06F9/4418 , G06F11/1469
摘要： A processing device boots or wakes using non-volatile logic element (NVL) array(s) that store a machine state. A standard boot sequence is used to restore a first portion of data. A second portion of data is restored, in parallel with the standard boot sequence, from the NVL array(s). A data corruption check is performed on the second portion of data. If the second data is valid, a standard boot sequence is used to restore a third portion of data. If the second data is invalid or the boot is an initial boot, a standard boot sequence is executed to determine the second portion of data, which is then stored in the NVL array(s). The processing device restores the second portion of the data during a portion of the boot/wake process that is not reading data from other non-volatile devices to avoid overloading the respective power domain.
摘要翻译：处理设备使用存储机器状态的非易失性逻辑元件（NVL）阵列引导或唤醒。标准引导顺序用于恢复数据的第一部分。数据的第二部分与标准引导序列并行地从NVL阵列恢复。对数据的第二部分执行数据损坏检查。如果第二个数据有效，则使用标准启动顺序恢复第三部分数据。如果第二数据无效或引导是初始引导，则执行标准引导序列以确定数据的第二部分，然后存储在NVL阵列中。处理设备在引导/唤醒处理的一部分期间恢复数据的第二部分，该部分未从其他非易失性设备读取数据，以避免相应的电源域超载。

4. 发明申请

US20160246355A1 Compute Through Power Loss Approach For Processing Device Having Nonvolatile Logic Memory 审中-公开
标题翻译：通过功率损耗方法计算具有非易失性逻辑存储器的处理器件
公开(公告)号：US20160246355A1
公开(公告)日：2016-08-25
申请号：US14918133
申请日：2015-10-20
申请人： Texas Instruments Incorporated , Texas Instruments Deutschland GmbH
发明人： Andreas Dannenberg , Brent Peterson , Aik K. Goh , Joerg Schreiner , Michael Zwerg , Steven Craig Bartling
IPC分类号： G06F1/32 , G06F9/44 , G06F12/02
CPC分类号： G06F1/3275 , G06F1/3243 , G06F1/3287 , G06F9/4418 , G06F12/0246 , G06F2212/7203 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/44 , Y02D50/20
摘要： A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.
摘要翻译：计算设备装置有助于使用深度低功率模式，其包括通过包括被配置为由CPU运行的软件例程来关闭设备的CPU，该软件程序将CPU和/或设备的状态保存到非易失性存储器外设进入深低功耗模式。响应于检测到低功率事件（即，足够运行CPU的功率损失）或软件命令进入深低功率模式以节省功率作为效率的一部分，可以配置软件例程来控制该状态存储程序。然后，从深度低功耗模式唤醒时，软件程序首先由CPU执行，以在执行中央处理单元的主应用程序之前从非易失性存储器恢复CPU和外围设备的状态。

5. 发明授权

US12087395B2 Customizable backup and restore from nonvolatile logic array 有权
公开(公告)号：US12087395B2
公开(公告)日：2024-09-10
申请号：US17558847
申请日：2021-12-22
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F1/00 , G06F1/3203 , G06F1/3234 , G06F1/3287 , G06F3/06 , G06F9/4401 , G06F11/10 , G06F11/14 , G06F12/02 , G06F13/00 , G11C7/22 , G11C14/00 , H03K3/3562
CPC分类号： G11C7/22 , G06F1/3203 , G06F1/3234 , G06F1/3275 , G06F1/3287 , G06F3/0679 , G06F3/0688 , G06F9/4401 , G06F9/4406 , G06F11/1032 , G06F11/1438 , G06F11/1469 , G06F12/0238 , G06F13/00 , G11C14/00 , H03K3/3562 , Y02D10/00 , Y02D30/50
摘要： Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

6. 发明授权

US11953969B2 Compute through power loss hardware approach for processing device having nonvolatile logic memory 有权
公开(公告)号：US11953969B2
公开(公告)日：2024-04-09
申请号：US17404125
申请日：2021-08-17
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Michael Zwerg , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F3/06 , G06F11/07
CPC分类号： G06F1/3293 , G06F1/3206 , G06F1/3287 , G06F3/061 , G06F3/0625 , G06F3/0634 , G06F3/0655 , G06F3/0656 , G06F3/0688 , G06F11/07 , Y02D10/00 , Y02D30/50
摘要： A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

7. 发明授权

US11847430B2 Non-volatile counter system, counter circuit and power management circuit with isolated dynamic boosted supply 有权
公开(公告)号：US11847430B2
公开(公告)日：2023-12-19
申请号：US17521019
申请日：2021-11-08
申请人： Texas Instruments Incorporated
发明人： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
IPC分类号： H03K5/00 , G06F7/62 , G06F1/30 , G06F1/26 , G08C13/02 , H03K5/24 , H03K21/40 , G11C11/56
CPC分类号： G06F7/62 , G06F1/26 , G06F1/30 , G08C13/02 , H03K5/24 , G11C11/56 , H03K21/40 , H03K21/403
摘要： Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

8. 发明申请

US20220057996A1 NON-VOLATILE COUNTER SYSTEM, COUNTER CIRCUIT AND POWER MANAGEMENT CIRCUIT WITH ISOLATED DYNAMIC BOOSTED SUPPLY 有权
公开(公告)号：US20220057996A1
公开(公告)日：2022-02-24
申请号：US17521019
申请日：2021-11-08
申请人： Texas Instruments Incorporated
发明人： Sudhanshu Khanna , Hao Meng , Michael Zwerg , Christy Leigh She , Steven Craig Bartling
IPC分类号： G06F7/62 , G06F1/30 , G06F1/26 , G08C13/02 , H03K5/24
摘要： Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

9. 发明授权

US11243903B2 Nonvolatile logic memory for computing module reconfiguration 有权
公开(公告)号：US11243903B2
公开(公告)日：2022-02-08
申请号：US16658928
申请日：2019-10-21
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Andreas Waechter , Mark Jung , Steven Craig Bartling , Sudhanshu Khanna
IPC分类号： G06F13/42 , G06F13/28 , H04L29/08
摘要： Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.

10. 发明授权

US10037071B2 Compute through power loss approach for processing device having nonvolatile logic memory 有权
公开(公告)号：US10037071B2
公开(公告)日：2018-07-31
申请号：US14918133
申请日：2015-10-20
申请人： Texas Instruments Incorporated
发明人： Andreas Dannenberg , Brent Peterson , Aik K. Goh , Joerg Schreiner , Michael Zwerg , Steven Craig Bartling
IPC分类号： G06F1/00 , G06F1/32 , G06F12/02 , G06F9/4401
CPC分类号： G06F1/3275 , G06F1/3243 , G06F1/3287 , G06F9/4418 , G06F12/0246 , G06F2212/7203 , Y02D10/14 , Y02D10/152 , Y02D10/171 , Y02D10/44 , Y02D50/20
摘要： A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a software routine configured to be run by the CPU that effects saving to a non-volatile memory a state of the CPU and/or the device's peripherals before entering the deep low-power mode. The software routine can be configured to control this state storage in response to detecting a low power event, i.e., loss of power sufficient to run the CPU, or a software command to enter the deep low power mode to save power as part of an efficiency program. Then, upon wake up from the deep low power mode, the software routine is first run by the CPU to effect restoring from the non-volatile memory the state of the CPU and the peripherals before execution of a primary application for the central processing unit.

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