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1. 发明授权

US09535123B2 Frequency scaled segmented scan chain for integrated circuits 有权
标题翻译：用于集成电路的频率分段扫描链
公开(公告)号：US09535123B2
公开(公告)日：2017-01-03
申请号：US14985699
申请日：2015-12-31
申请人： Texas Instruments Incorporated
发明人： Rajesh Kumar Mittal , Wilson Pradeep , Vivek Singhal
IPC分类号： G01R31/3177 , G01R31/28 , G01R31/317 , G01R31/44
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31721 , G01R31/31725 , G01R31/318538 , G01R31/318563 , G01R31/318575
摘要： A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.
摘要翻译：扫描链可以形成在整个集成电路中，其中扫描链包括至少第一段和第二段。通过以奇数时钟对第一段中的多个扫描单元的其余部分进行计时，同时以奇数时钟计时第一段的第一扫描单元，将测试图案的第一部分扫描到第一段中，其中奇数时钟与偶数时钟异相，其中偶数时钟和奇数时钟具有等于测试图案的扫描速率除以整数N的速率。测试图案的第二部分被扫描到第二段中以奇数时钟对第二段中的多个扫描单元进行计时，使得测试图案的第二部分不被扫描到第一段中。

2. 发明申请

US20210215757A1 Full Pad Coverage Boundary Scan 有权
公开(公告)号：US20210215757A1
公开(公告)日：2021-07-15
申请号：US17217391
申请日：2021-03-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Prakash Narayanan , Rajesh Kumar Mittal , Rajat Mehrotra
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185
摘要： An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

3. 发明授权

US10983161B2 Full pad coverage boundary scan 有权
公开(公告)号：US10983161B2
公开(公告)日：2021-04-20
申请号：US16380182
申请日：2019-04-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Prakash Narayanan , Rajesh Kumar Mittal , Rajat Mehrotra
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3177
摘要： An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

4. 发明申请

US20160131704A1 SCAN THROUGHPUT ENHANCEMENT IN SCAN TESTING OF A DEVICE-UNDER-TEST 有权
标题翻译：扫描测试中的设备测试的扫描增强
公开(公告)号：US20160131704A1
公开(公告)日：2016-05-12
申请号：US14539555
申请日：2014-11-12
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mudasir Shafat Kawoosa , Rajesh Kumar Mittal , Sreenath Narayanan Potty
IPC分类号： G01R31/3177
CPC分类号： G11C29/12 , G01R31/28 , G01R31/318563 , G11C29/32
摘要： Systems and methods for enabling scan testing of device-under-test (DUT) are disclosed. In an embodiment, a test system for scan testing the DUT, including P scan input ports and Q scan output ports, includes tester and adapter module. Tester operates at clock frequency F1 and includes M tester Input/Output (I/O) ports for providing M scan inputs and N tester I/O ports for receiving N scan outputs at F1. Adapter module is coupled to tester and configured to receive M scan inputs at F1 and, in response, provide P scan inputs at clock frequency F2 to P scan input ports, and to receive Q scan outputs at F2 from Q scan output ports and, in response, provide N scan outputs at F1 to N tester I/O ports, where ratio of M to P equals ratio of N to Q, and where each of M, N, P and Q are positive integers.
摘要翻译：公开了用于启用被测器件（DUT）的扫描测试的系统和方法。在一个实施例中，用于扫描测试DUT的测试系统，包括P扫描输入端口和Q扫描输出端口，包括测试器和适配器模块。测试仪以时钟频率F1工作，并包括M测试仪输入/输出（I / O）端口，用于提供M扫描输入和N个测试仪I / O端口，用于在F1接收N个扫描输出。适配器模块耦合到测试器，并配置为在F1接收M个扫描输入，作为响应，在时钟频率F2提供P扫描输入到P扫描输入端口，并从Q扫描输出端口接收F2的Q扫描输出，并在响应，在F1到N测试仪I / O端口提供N个扫描输出，其中M与P的比值等于N与Q的比率，并且其中M，N，P和Q中的每一个是正整数。

5. 发明授权

US09261560B2 Handling slower scan outputs at optimal frequency 有权
标题翻译：以最佳频率处理较慢的扫描输出
公开(公告)号：US09261560B2
公开(公告)日：2016-02-16
申请号：US14145293
申请日：2013-12-31
申请人： Texas Instruments Incorporated
发明人： Rajesh Kumar Mittal , Mudasir Shafat Kawoosa , Sreenath Narayanan Potty
IPC分类号： G01R31/3183 , G01R31/3177 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/318335 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318547 , G01R31/318552
摘要： An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements. Each packing element includes k number of flip-flops. Each flip-flop of the k number of flip-flops receives a scan output of the M scan outputs and a phase-shifted scan clock of the k number of phase-shifted scan clocks, and generates a slow scan output of the kM slow scan outputs.
摘要翻译：实施例提供了一种用于测试集成电路的电路。该电路包括由扫描时钟驱动的扫描压缩架构并产生M个扫描输出，其中M是整数。时钟分频器被配置为将扫描时钟除以k以产生k个相移扫描时钟，其中k是整数。打包逻辑耦合到扫描压缩架构，并响应于M扫描输出和k个相移扫描时钟产生kM慢速扫描输出。包装逻辑还包括M个包装元件。每个包装元件包括k个触发器。 k个触发器的每个触发器接收M个扫描输出的扫描输出和k个相移扫描时钟的相移扫描时钟，并且生成kM慢扫描的慢速扫描输出输出。

6. 发明授权

US10877093B2 Non-interleaved scan operation for achieving higher scan throughput in presence of slower scan outputs 有权
公开(公告)号：US10877093B2
公开(公告)日：2020-12-29
申请号：US16117644
申请日：2018-08-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mudasir Shafat Kawoosa , Rajesh Kumar Mittal
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/28 , G01R31/317
CPC分类号： G01R31/3177 , G01R31/2851 , G01R31/31713 , G01R31/31723 , G01R31/318572 , G01R31/318594
摘要： A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

7. 发明申请

US20190235020A1 Full Pad Coverage Boundary Scan 审中-公开
公开(公告)号：US20190235020A1
公开(公告)日：2019-08-01
申请号：US16380182
申请日：2019-04-10
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Prakash Narayanan , Rajesh Kumar Mittal , Rajat Mehrotra
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/31713 , G01R31/3177 , G01R31/318536 , G01R31/318572
摘要： An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

8. 发明申请

US20150185283A1 HANDLING SLOWER SCAN OUTPUTS AT OPTIMAL FREQUENCY 有权
标题翻译：以最佳频率处理SLAN SCAN输出
公开(公告)号：US20150185283A1
公开(公告)日：2015-07-02
申请号：US14145293
申请日：2013-12-31
申请人： Texas Instruments Incorporated
发明人： Rajesh Kumar Mittal , Mudasir Shafat Kawoosa , Sreenath Narayanan Potty
IPC分类号： G01R31/3177 , G01R31/317
CPC分类号： G01R31/318335 , G01R31/31725 , G01R31/31727 , G01R31/3177 , G01R31/318547 , G01R31/318552
摘要： An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements and each packing element of the M number of packing elements receives a scan output of the M scan outputs. Each packing element includes k number of flip-flops and each flip-flop of the k number of flip-flops in a packing element receives a scan output of the M scan outputs. Each flip-flop receives a phase-shifted scan clock of the k number of phase-shifted scan clocks, such that each flip-flop generates a slow scan output of the kM slow scan outputs in response to the scan output and the phase-shifted scan clock.
摘要翻译：实施例提供了一种用于测试集成电路的电路。该电路包括由扫描时钟驱动的扫描压缩架构并产生M个扫描输出，其中M是整数。时钟分频器被配置为将扫描时钟除以k以产生k个相移扫描时钟，其中k是整数。打包逻辑耦合到扫描压缩架构，并响应于M扫描输出和k个相移扫描时钟产生kM慢速扫描输出。包装逻辑还包括M个包装元件，并且M个包装元件的每个包装元件接收M个扫描输出的扫描输出。每个封装元件包括k个触发器，并且打包元件中k个触发器的每个触发器接收M个扫描输出的扫描输出。每个触发器接收k个相移扫描时钟的相移扫描时钟，使得每个触发器响应于扫描输出和相移而产生kM慢扫描输出的慢扫描输出扫描时钟。

9. 发明申请

US20140232422A1 BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE 审中-公开
标题翻译：内置自测试方法，电路和装置，用于具有动态可配置的测试结构的RF模块的同时测试
公开(公告)号：US20140232422A1
公开(公告)日：2014-08-21
申请号：US14179046
申请日：2014-02-12
申请人： Texas Instruments Incorporated
发明人： Adesh Sontakke , Rajesh Kumar Mittal , Rubin A. Parekhji , Upendra Narayan Tripathi
IPC分类号： G01R31/319
CPC分类号： G01R31/31917 , G01R31/31716 , G01R31/31724
摘要： A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.
摘要翻译：可测试的集成电路芯片（80,100）包括具有模块（IP.i）的功能电路（80），存储电路（110），其可操作以保持表示兼容兼容的兼容测试集合的表，以及on 与所述存储电路（110）和所述功能电路模块（IP.i）耦合的芯片测试控制器（140,150），所述测试控制器（140,150）可操作以动态地调度和触发这些组中的测试，由此促进在所述功能电路模块（IP.i）中并行执行测试。公开了其他电路，无线芯片，系统以及操作过程和制造过程。

10. 发明申请

US20180372798A1 NON-INTERLEAVED SCAN OPERATION FOR ACHIEVING HIGHER SCAN THROUGHPUT IN PRESENCE OF SLOWER SCAN OUTPUTS 审中-公开
公开(公告)号：US20180372798A1
公开(公告)日：2018-12-27
申请号：US16117644
申请日：2018-08-30
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Mudasir Shafat Kawoosa , Rajesh Kumar Mittal
IPC分类号： G01R31/3177 , G01R31/3185 , G01R31/28 , G01R31/317
摘要： A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

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