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1. 发明授权

US11183460B2 Embedded die packaging with integrated ceramic substrate 有权
公开(公告)号：US11183460B2
公开(公告)日：2021-11-23
申请号：US16132906
申请日：2018-09-17
申请人： Texas Instruments Incorporated
发明人： Woochan Kim , Mutsumi Masumoto , Kengo Aoya , Vivek Kishorechand Arora , Anindya Poddar
IPC分类号： H01L23/538 , H01L23/373 , H01L21/56 , H01L23/498
摘要： Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

2. 发明申请

US20150147845A1 DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND 审中-公开
标题翻译：双面嵌入式电池及其制造方法背景
公开(公告)号：US20150147845A1
公开(公告)日：2015-05-28
申请号：US14552548
申请日：2014-11-25
申请人： Texas Instruments Incorporated
发明人： Anindya Poddar , Mark Allen Gerber , Mutsumi Masumoto , Masamitsu Matsuura , Kengo Aoya , Takeshi Onogami
IPC分类号： H01L25/00 , H01L21/304 , H01L21/683 , H01L21/3213 , H01L21/321 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/561 , H01L21/4857 , H01L21/568 , H01L21/6836 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2221/68327 , H01L2221/68345 , H01L2224/04105 , H01L2924/12042 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.
摘要翻译：本发明的实施例提供了一种用于形成双面嵌入式模具系统的方法。该方法从起始材料开始，包括顶表面和底表面，多个通孔，多个电镀金属柱，冲压垫和加强件。将表面平坦化以暴露所包含的金属，其不是从管芯附着垫DAP区域选择性地蚀刻以形成空腔。通过使用光刻胶图案和电镀创建一个加强筋。涂抹胶带。附上一个模具层压和研磨。去除胶带。形式重新分配层RDL和焊接掩模。安装表面贴装器件。

3. 发明授权

US11410875B2 Fan-out electronic device 有权
公开(公告)号：US11410875B2
公开(公告)日：2022-08-09
申请号：US16225875
申请日：2018-12-19
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Hau Thanh Nguyen , Woochan Kim , Yi Yan , Luu Thanh Nguyen , Ashok Prabhu , Anindya Poddar , Masamitsu Matsuura , Kengo Aoya , Mutsumi Masumoto
IPC分类号： H01L21/768 , H01L23/528 , H01L23/31 , H01L23/00
摘要： An electronic device (100) includes a substrate (110) and an integrated circuit (120) provided on the substrate (110) having a surface facing away from the substrate (110). An insulating layer (150) extends over the substrate (110) and around the integrated circuit (120) to define an interface (154) between the insulating layer (150) and the integrated circuit (120). An electrically conductive via (130) is provided on the surface of the integrated circuit (120). An insulating material (140) extends over the via (130) and includes an opening (142) exposing a portion of the via (130). A repassivation member (162) extends over the insulating layer (150) and has a surface (164) aligned with the interface (154). An electrically conductive redistribution member (181) is electrically connected to the via (130) and extends over the repassivation member (162) into contact with the insulating layer (150).

4. 发明授权

US11183441B2 Stress buffer layer in embedded package 有权
公开(公告)号：US11183441B2
公开(公告)日：2021-11-23
申请号：US16808018
申请日：2020-03-03
申请人： Texas Instruments Incorporated
发明人： Woochan Kim , Masamitsu Matsuura , Mutsumi Masumoto , Kengo Aoya , Hau Thanh Nguyen , Vivek Kishorechand Arora , Anindya Poddar
IPC分类号： H01L23/10 , H01L23/34 , H01L23/367 , H01L21/56 , H01L23/00 , H01L23/373
摘要： The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

5. 发明申请

US20190385924A1 Stress Buffer Layer in Embedded Package 审中-公开
公开(公告)号：US20190385924A1
公开(公告)日：2019-12-19
申请号：US16008119
申请日：2018-06-14
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Woochan Kim , Masamitsu Matsuura , Mutsumi Masumoto , Kengo Aoya , Hau Thanh Nguyen , Vivek Kishorechand Arora , Anindya Poddar
IPC分类号： H01L23/367 , H01L21/56 , H01L23/00
摘要： The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

6. 发明申请

US20160240392A1 DUAL SIDED EMBEDDED DIE AND FABRICATION OF SAME BACKGROUND 审中-公开
公开(公告)号：US20160240392A1
公开(公告)日：2016-08-18
申请号：US15137114
申请日：2016-04-25
申请人： Texas Instruments Incorporated
发明人： Anindya Poddar , Mark Allen Gerber , Mutsumi Masumoto , Masamitsu Matsuura , Kengo Aoya , Takeshi Onogami
IPC分类号： H01L21/56 , H01L21/48
CPC分类号： H01L21/561 , H01L21/4857 , H01L21/568 , H01L21/6836 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2221/68327 , H01L2221/68345 , H01L2224/04105 , H01L2924/12042 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： Embodiments of the invention provide a method for forming a dual sided embedded die system. The method begins with starting material including a top surface and a bottom surface, a plurality of vias, a plurality of plated metal posts, die pads, and stiffeners. The surface are planarized to expose the included metal which is than selectively etching from die attach pad DAP areas to form cavities. Create a stiffener by using photo resist patterning and plating. Apply tacky tape. Attach a die. Laminate and grind. Remove tacky tape. Form redistribution layers RDLs and a solder mask. Mounting Surface Mount Devices.

7. 发明申请

US20140069989A1 Thin Semiconductor Chip Mounting 审中-公开
标题翻译：薄半导体芯片安装
公开(公告)号：US20140069989A1
公开(公告)日：2014-03-13
申请号：US14024803
申请日：2013-09-12
申请人： Texas Instruments Incorporated
发明人： Mutsumi Masumoto
IPC分类号： H01L21/50
CPC分类号： H01L21/50 , H01L24/75 , H01L24/81 , H01L2224/13144 , H01L2224/75303 , H01L2224/75317 , H01L2224/75745 , H01L2224/81121 , H01L2224/81191 , H01L2224/81203 , H01L2924/10253 , Y10T156/1168 , H01L2924/00 , H01L2924/00014
摘要： The embodiments of the invention provide a semiconductor chip mounting methods to prevent the occurrence of particles created while mounting a thin semiconductor chip onto a substrate. A semiconductor chip having conductive bumps on its main surface is held by its back via an elastic film using a suction tool having a plurality of suction holes, the semiconductor chip is positioned against a substrate provided with connection wires corresponding to said conductive bumps, and the semiconductor chip is mounted onto the substrate in such a manner that the conductive bumps connect to said connection wires, and uniform pressure is applied from the oversized bonding tool suction to the semiconductor chip via said film while said semiconductor chip is being pressed against said substrate by oversized bonding tool to keep constant pressure in order to bond said conductive bumps with said connection wires. The film assisted bonding tool has a film cooling system to assist in making vacuum holes and a through-hole tool movable relative to the bonding head to create a plurality of holes in said assist film with a plurality of needles.
摘要翻译：本发明的实施例提供一种半导体芯片安装方法，以防止在将薄半导体芯片安装到基板上时产生的颗粒的出现。在其主表面上具有导电凸块的半导体芯片通过使用具有多个吸孔的抽吸工具通过弹性膜由其背面保持，半导体芯片位于与设置有与所述导电凸块相对应的连接线的基板上，将半导体芯片以这样的方式安装到基板上，使得导电凸块连接到所述连接线，并且通过所述薄膜将超大的焊接工具抽吸均匀地施加到半导体芯片上，同时所述半导体芯片被所述衬底压靠在所述衬底上超大的焊接工具以保持恒定的压力，以便将所述导电凸块与所述连接线接合。薄膜辅助粘结工具具有薄膜冷却系统，以帮助制造真空孔，并且通孔工具相对于粘合头可移动，以在多个针中在所述辅助薄膜中产生多个孔。

8. 发明授权

US11158595B2 Embedded die package multichip module 有权
公开(公告)号：US11158595B2
公开(公告)日：2021-10-26
申请号：US16028741
申请日：2018-07-06
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Woochan Kim , Masamitsu Matsuura , Mutsumi Masumoto , Kengo Aoya , Hau Thanh Nguyen , Vivek Kishorechand Arora , Anindya Poddar
IPC分类号： H01L23/48 , H01L23/00 , H01L25/065 , H01L23/532 , H01L21/56 , H01L23/31 , H01L25/00 , H01L23/29 , H01L23/528 , H01L23/522 , H01L23/538 , H01L23/433 , H01L23/367
摘要： An embedded die package includes a first die having an operating voltage between a first voltage potential and a second voltage potential that is less than the first voltage potential. A via, including a conductive material, is electrically connected to a bond pad on a surface of the first die, the via including at least one extension perpendicular to a plane along a length of the via. A redistribution layer (RDL) is electrically connected to the via, at an angle with respect to the via defining a space between the surface and a surface of the RDL. A build-up material is in the space.

9. 发明申请

US20210134729A1 FRAME DESIGN IN EMBEDDED DIE PACKAGE 有权
公开(公告)号：US20210134729A1
公开(公告)日：2021-05-06
申请号：US16669666
申请日：2019-10-31
申请人： Texas Instruments Incorporated
发明人： Woochan Kim , Masamitsu Matasuura , Mutsumi Masumoto , Kengo Aoya , Hau Thanh Nguyen , Vivek Kishorechand Arora , Anindya Poddar , Hideaki Matsunaga
IPC分类号： H01L23/538 , H01L23/31 , H01L23/00 , H01L21/56 , H01L21/48
摘要： In one example, embedded die package, including a layer having an exposed boundary, wherein at least a portion of the exposed boundary comprises organic material. The package also includes at least one integrated circuit die positioned in the layer and within the exposed boundary. The package also includes a dielectric material positioned in the layer and between the at least one integrated circuit and structure adjacent the at least one integrated circuit.

10. 发明申请

US20160005705A1 Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips 审中-公开
标题翻译：嵌入式半导体芯片批量封装低引脚数的结构与方法
公开(公告)号：US20160005705A1
公开(公告)日：2016-01-07
申请号：US14320825
申请日：2014-07-01
申请人： Texas Instruments Incorporated
发明人： Mutsumi Masumoto
IPC分类号： H01L23/00 , H01L23/31 , H01L21/56 , H01L21/3105 , H01L21/78
摘要： A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.
摘要翻译：一种以面板格式制造封装半导体器件的方法。用于一组连续的芯片的平板尺寸包括绝缘板的刚性基板和具有可在高温下可释放的第一粘合剂的表面层的带，芯基膜和具有第二粘合剂的底层到基底。将一组固定在第一粘合剂层上，芯片端子具有金属凸块背离第一粘合剂层的端子。层压低CTE绝缘材料以填充凸块之间的间隙并形成围绕该组的绝缘框架。研磨层压材料以暴露凸块。等离子体清洁组件，跨组装溅射均匀的金属层，可选地镀覆金属层，以及图案化金属层以形成重新路由迹线和扩展的接触焊盘。

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