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1. 发明授权

US11469784B2 Spur estimating receiver system 有权
公开(公告)号：US11469784B2
公开(公告)日：2022-10-11
申请号：US17001157
申请日：2020-08-24
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Aswath Vs , Sthanunathan Ramakrishnan , Sriram Murali , Sarma Sundareswara Gunturi , Jaiganesh Balakrishnan , Sashidharan Venkatraman
IPC分类号： H04B1/10 , H04B1/16
摘要： One example includes a receiver system. The receiver system includes an analog-to-digital converter (ADC) configured to convert an analog input signal into a digital output signal at a sampling frequency. The receiver system also includes a spur correction system configured to receive the digital output signal and to estimate spurs associated with the digital output signal and to selectively correct a subset of the spurs associated with a set of frequencies that are based on the sampling frequency.

2. 发明授权

US11171674B2 Low-complexity inverse sinc for RF sampling transmitters 有权
公开(公告)号：US11171674B2
公开(公告)日：2021-11-09
申请号：US17022871
申请日：2020-09-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jaiganesh Balakrishnan , Sriram Murali , Sundarrajan Rangachari , Yeswanth Guntupalli
IPC分类号： H04L5/12 , H04L23/02 , H04B1/00
摘要： A radio-frequency (RF) sampling transmitter (e.g., of the type that may be used in 5G wireless base stations) includes a complex baseband digital-to-analog converter (DAC) response compensator that operates on a complex baseband signal at a sampling rate lower than the sampling rate of an RF sampling DAC in the RF sampling transmitter. The DAC response compensator flattens the sample-and-hold response of the RF sampling DAC only in the passband of interest, addressing the problem of a sinc response introduced by the sample-and-hold operation of the RF sampling DAC and avoiding the architectural complexity and high power consumption of an inverse sinc filter that operates on the signal at a point in the signal chain after it has already been up-converted to an RF passband.

3. 发明申请

US20200313944A1 IQ MISMATCH CORRECTION FOR ZERO-IF/LOW-IF TX/RX 审中-公开
公开(公告)号：US20200313944A1
公开(公告)日：2020-10-01
申请号：US16902529
申请日：2020-06-16
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Jaiganesh Balakrishnan
IPC分类号： H04L27/20 , H04B1/40 , H04L27/22
摘要： IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.

4. 发明授权

US10741268B2 Flexible and efficient device trim support using efuse 有权
公开(公告)号：US10741268B2
公开(公告)日：2020-08-11
申请号：US16235698
申请日：2018-12-28
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Aravind Ganesan , Jaiganesh Balakrishnan , Nagarajan Viswanathan , Yeswanth Guntupalli , Ajai Paulose , Mathews John , Jagannathan Venkataraman , Neeraj Shrivastava
IPC分类号： G11C29/02 , G11C17/14 , G11C17/16 , G11C17/18
摘要： A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

5. 发明授权

US10715376B2 Enhanced IQ mismatch correction function generator 有权
公开(公告)号：US10715376B2
公开(公告)日：2020-07-14
申请号：US16444035
申请日：2019-06-18
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jaiganesh Balakrishnan , Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Chandrasekhar Sriram
IPC分类号： H03D1/04 , H04L27/38 , H04B1/30 , H04L27/26 , H04L27/36
摘要： An IQ mismatch correction function generator configured to generate an enhanced IQ mismatch correction function to improve the compensation for IQ mismatch, and an IQ signal receiver with the IQ mismatch correction function generator, wherein the enhanced IQ mismatch correction function is determined based on an initial IQ mismatch correction function derived from IQ mismatch estimates corresponding to frequency bins where signals are present and error of the initial IQ mismatch correction function by comparing the values of the initial IQ mismatch correction function with IQ mismatch estimates corresponding to a respective bin of the frequency bins.

6. 发明授权

US10635396B2 Internally truncated multiplier 有权
公开(公告)号：US10635396B2
公开(公告)日：2020-04-28
申请号：US16454369
申请日：2019-06-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jawaharlal Tangudu , Suvam Nandi , Pooja Sundar , Jaiganesh Balakrishnan
IPC分类号： G06F7/533 , G06F7/523 , G06F7/50 , H03D7/16
CPC分类号： G06F7/523 , G06F7/50 , H03D7/161
摘要： A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

7. 发明授权

US10541703B2 Interleaved ADC with estimation of DSA-setting-based IL mismatch 有权
公开(公告)号：US10541703B2
公开(公告)日：2020-01-21
申请号：US16029539
申请日：2018-07-06
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Sthanunathan Ramakrishnan , Sashidharan Venkatraman , Jaiganesh Balakrishnan , Sreenath Narayanan Potty
IPC分类号： H03M1/12 , H03F1/02 , H03M1/06
摘要： An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy.

8. 发明授权

US10372415B2 Internally truncated multiplier 有权
公开(公告)号：US10372415B2
公开(公告)日：2019-08-06
申请号：US15587096
申请日：2017-05-04
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jawaharlal Tangudu , Suvam Nandi , Pooja Sundar , Jaiganesh Balakrishnan
IPC分类号： G06F7/533 , G06F7/523 , G06F7/50 , H03D7/16
摘要： A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

9. 发明申请

US20190214972A1 METHODS AND APPARATUS FOR EFFICIENT LINEAR COMBINER 审中-公开
公开(公告)号：US20190214972A1
公开(公告)日：2019-07-11
申请号：US16299299
申请日：2019-03-12
申请人： Texas Instruments Incorporated
发明人： Jaiganesh Balakrishnan , Sthanunathan Ramakrishnan , Pooja Sundar , Sashidharan Venkatraman
IPC分类号： H03H17/02 , G06F5/01 , H03M1/06 , G06F7/544 , H03H17/00 , H03H17/06
CPC分类号： H03H17/0219 , G06F5/01 , G06F7/5443 , H03H17/0045 , H03H17/06 , H03M1/0626 , H03M1/12 , H03M1/1215
摘要： In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

10. 发明授权

US10341082B1 Delay modulated clock division 有权
公开(公告)号：US10341082B1
公开(公告)日：2019-07-02
申请号：US15906000
申请日：2018-02-27
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： Jaiganesh Balakrishnan , Shagun Dusad , Visvesvaraya Pentakota , Srinivas Kumar Reddy Naru , Sarma Sundareswara Gunturi , Nagalinga Swamy Basayya Aremallapur
IPC分类号： H04L7/00 , H03K5/14 , H03K5/00 , H04L9/32
摘要： A clock divider comprises a clock delay line that comprises a plurality of delay elements, a clock delay selector coupled to the clock delay line and configured to select one of the plurality of delay elements and a bit pattern source coupled to the clock delay selector. The clock delay line is configured to generate a modulated divided clock signal with a suppressed fundamental spectral component.

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