专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09444413B2 High bandwidth amplifier 有权
标题翻译：高带宽放大器
公开(公告)号：US09444413B2
公开(公告)日：2016-09-13
申请号：US14432759
申请日：2015-02-04
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03F3/68 , H03F1/42 , H03F3/19 , H03F3/60
CPC分类号： H03F1/42 , H03F1/08 , H03F1/223 , H03F3/19 , H03F3/193 , H03F3/605 , H03F3/68 , H03F2200/36 , H03F2200/451
摘要： An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor (M4) coupled to the first output (22), a second terminal (T42) of the fourth transistor (M4) coupled to a fourth voltage rail (24), and a gate (G4) of the fourth transistor (M4) coupled to the second terminal (T32) of the third transistor (M3); and a first capacitive element (C1) coupled between the second terminal (T32) of the third transistor (M3) and the first output (22).

2. 发明授权

US09407478B1 Low power and area bootstrapped passive mixer with shared capacitances 有权
标题翻译：低功率和区域自举无源混频器具有共享电容
公开(公告)号：US09407478B1
公开(公告)日：2016-08-02
申请号：US14838044
申请日：2015-08-27
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03D7/14 , H04L25/08 , H04B1/10
CPC分类号： H04L25/08 , H03D7/1441 , H03D7/1458 , H03D7/1466 , H03D7/165
摘要： In a passive mixer, switches and a capacitance are shared between bootstrapped mixing transistors, reducing the number of components required as compared to prior art bootstrap designs. Shared bootstrap circuits operate in an interleaved fashion between I and Q mixer circuits, at twice the LO frequency. That is, the shared bootstrap circuits in each I mixer circuit charge their capacitors in a first half-period of a clock, and connect the shared capacitor to the gate of an enabled mixing transistor in the second half-period. The shared bootstrap circuits in the Q mixer circuit charge their capacitors in the second half-period, and connect the shared capacitor to the gate of an enabled mixing transistor in the first half-period. One of two mixing transistors connected to each shared bootstrap circuit is alternately enabled during the clock signal half-periods that the shared bootstrap circuit is not charging its capacitor.
摘要翻译：在无源混频器中，开关和电容在自举混频晶体管之间共享，与现有技术的引导设计相比，减少了所需的部件数量。共享引导电路在I和Q混频器电路之间以交错方式工作，为LO频率的两倍。也就是说，每个I混频器电路中的共享自举电路在其第一个半周期内对其电容器充电，并在第二个半周期内将共享电容连接到启用的混合晶体管的栅极。 Q混频器电路中的共享引导电路在后半段对其电容充电，并在上半个周期内将共享电容连接到启用的混合晶体管的栅极。在共享自举电路未对其电容器充电的时钟信号半周期期间，连接到每个共享自举电路的两个混合晶体管中的一个交替使能。

3. 发明申请

US20160226454A1 High Bandwidth Amplifier 有权
标题翻译：高带宽放大器
公开(公告)号：US20160226454A1
公开(公告)日：2016-08-04
申请号：US14432759
申请日：2015-02-04
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03F1/42 , H03F3/19
CPC分类号： H03F1/42 , H03F1/08 , H03F1/223 , H03F3/19 , H03F3/193 , H03F3/605 , H03F3/68 , H03F2200/36 , H03F2200/451
摘要： An amplifier (100) comprising: first, second, third and fourth transistors (M1, M2, M3, M4), an input (10) for an input signal, and a first output (22) for a first amplified signal; a first terminal (T11) of the first transistor (M1) coupled to a first voltage rail (12), a second terminal (T12) of the first transistor (M1) coupled to a first terminal (T31) of the third transistor (M3), and a gate (G1) of the first transistor (M1) coupled to the input (10); a first terminal (T21) of the second transistor (M2) coupled to a second voltage rail (14), a second terminal (T22) of the second transistor (M2) coupled to the first output (22), and a gate (G2) of the second transistor (M2) coupled to the input (10); a load (40) coupled between a second terminal (T32) of the third transistor (M3) and a third voltage rail (20), and a gate (G3) of the third transistor (M3) coupled to a bias node (16) for applying a bias voltage to the gate (G3) of the third transistor (M3); a first terminal (T41) of the fourth transistor (M4) coupled to the first output (22), a second terminal (T42) of the fourth transistor (M4) coupled to a fourth voltage rail (24), and a gate (G4) of the fourth transistor (M4) coupled to the second terminal (T32) of the third transistor (M3); and a first capacitive element (C1) coupled between the second terminal (T32) of the third transistor (M3) and the first output (22).
摘要翻译：一种放大器，包括：第一，第二，第三和第四晶体管（M1，M2，M3，M4），用于输入信号的输入端（10）和用于第一放大信号的第一输出端（22）耦合到第一电压轨（12）的第一晶体管（M1）的第一端（T11），耦合到第三晶体管（M3）的第一端（T31）的第一晶体管（M1）的第二端（T12））和耦合到输入（10）的第一晶体管（M1）的栅极（G1）; 耦合到第二电压轨（14）的第二晶体管（M2）的第一端子（T21），耦合到第一输出端（22）的第二晶体管（M2）的第二端子（T22）和栅极）耦合到所述输入（10）的所述第二晶体管（M2）; 耦合在第三晶体管（M3）的第二端子（T32）和第三电压轨道（20）之间的负载（40）和耦合到偏置节点（16）的第三晶体管（M3）的栅极（G3）用于向第三晶体管（M3）的栅极（G3）施加偏置电压; 耦合到第一输出端（22）的第四晶体管（M4）的第一端子（T41），耦合到第四电压轨道（24）的第四晶体管（M4）的第二端子（T42）和栅极）连接到第三晶体管（M3）的第二端子（T32）的第四晶体管（M4）; 以及耦合在第三晶体管（M3）的第二端子（T32）和第一输出端（22）之间的第一电容元件（C1）。

4. 发明授权

US09401727B1 Shared circuit configurations for bootstrapped sample and hold circuits in a time-interleaved analog to digital converter 有权
标题翻译：在时间交织的模数转换器中自举采样和保持电路的共享电路配置
公开(公告)号：US09401727B1
公开(公告)日：2016-07-26
申请号：US14838012
申请日：2015-08-27
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Mattias Palm , Roland Strandberg
IPC分类号： H03M1/12 , G11C27/02 , H03K17/06 , H03M1/00 , H03M1/08
CPC分类号： H03M1/1245 , G11C27/024 , H03K17/063 , H03M1/002 , H03M1/0845 , H03M1/1215
摘要： In a time-interleaved Analog to Digital Converter, circuit components and capacitances may be shared among a plurality of sample and hold circuits in each of two sets. The two shared circuits alternate, on different half-periods of a master clock signal, between charging a capacitance and sampling an input in an overlapping manner such that one is charging while the other is sampling. One sample and hold circuit is activated during each successive half-period (following a charging half-period) by independent, sequential, non-overlapping clocking signals. To improve SNDR, at least one switch is bootstrapped by driving its gate terminal with the voltage of a capacitor configured between the gate and the input signal. By sharing at least some components among multiple sample and hold circuits, the number of gates driven by clock signals is reduced, reducing clock distribution and calibration complexity, and the circuit area is reduced.
摘要翻译：在时间交织的模数转换器中，电路组件和电容可以在两组中的每一组中的多个采样和保持电路之间共享。两个共享电路在主时钟信号的不同半周期间交替地在对电容进行充电和以重叠的方式对输入进行采样之间进行交替，使得一个充电而另一个正在进行采样。一个采样和保持电路通过独立的，顺序的，不重叠的时钟信号在每个连续的半周期（在充电半周期之后）被激活。为了改善SNDR，通过在栅极和输入信号之间配置的电容器的电压驱动其栅极端子，至少一个开关被自举。通过在多个采样和保持电路中共享至少一些组件，减少了由时钟信号驱动的门数，减少了时钟分布和校准复杂度，并且减少了电路面积。

5. 发明授权

US09806677B2 Amplifier adapted for noise suppression 有权
公开(公告)号：US09806677B2
公开(公告)日：2017-10-31
申请号：US14913466
申请日：2015-03-16
申请人： Telefonaktiebolaget L M Ericsson (publ)
发明人： Daniele Mastantuono , Sven Mattisson
IPC分类号： H03F3/45 , H03F1/26 , H03F1/32 , H03F3/193 , H03F1/02 , H03F1/48 , H03F3/60 , H04B1/12
CPC分类号： H03F1/26 , H03F1/0205 , H03F1/3211 , H03F1/483 , H03F3/193 , H03F3/45179 , H03F3/607 , H03F2200/06 , H03F2200/294 , H03F2200/333 , H03F2200/451 , H03F2203/45306 , H03F2203/45318 , H04B1/12
摘要： An amplifier (100) adapted for noise suppression comprises a first input (102) for receiving a first input signal and a second input (104) for receiving a second input signal, the first and second input signals constituting a differential pair. A first output (106) delivers a first output signal and a second output (108) delivers a second output signal, the first and second output signals constituting a differential pair. A first transistor (MCG1) has a first drain (110) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the first drain (110) flows through the first output (106), and the first transistor (MCG1) further having a first source (112) coupled to the first input (102). A second transistor (MCS1) has a second gate (116) coupled to the first input (102), a second drain (118) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the second drain (118) flows through the second output (108), and the second transistor (MCS1) further having a second source (120) coupled to a first voltage rail (122). A third transistor (MCS2) has a third gate (124) coupled to the second input (104), a third drain (126) coupled to the first output (106) such that all signal current, except parasitic losses, flowing through the third drain (126) flows through the first output (106), and the third transistor (MCS2) further having a third source (128) coupled to the first voltage rail (122). A fourth transistor (MCG2) has a fourth drain (130) coupled to the second output (108) such that all signal current, except parasitic losses, flowing through the fourth drain (130) flows through the second output (108), and the fourth transistor (MCG2) further having a fourth source (132) coupled to the second input (104). A first load (ZL1) is coupled between the first output (106) and a second voltage rail (136). A second load (ZL2) is coupled between the second output (108) and the second voltage rail (136). A first inductive element (L1) is coupled between the first input (102) and a third voltage rail (138), and a second inductive element (L2) is coupled between the second input (104) and the third voltage rail (138). Transconductance of the first transistor (MCG1) is substantially equal to transconductance of the fourth transistor (MCG2), within ±5%, and transconductance of the second transistor (MCS1) is substantially equal to transconductance of the third transistor (MCS2), within ±5%.

6. 发明申请

US20160126912A1 Attenuator Control for a Signal Processing Chain 审中-公开
标题翻译：信号处理链的衰减器控制
公开(公告)号：US20160126912A1
公开(公告)日：2016-05-05
申请号：US14896633
申请日：2013-06-13
申请人： TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
发明人： Lars Sundström , Daniele Mastantuono , Sven Mattison , Roland Strandberg
IPC分类号： H03G3/30
CPC分类号： H03G3/3036 , H03G1/0088 , H03G3/3052
摘要： An attenuator control method of a signal processing chain comprising two or more signal processing units is disclosed. One of the two or more signal processing units is a signal attenuator adapted to apply adaptive signal attenuation of an attenuator input signal based on one or more attenuation parameters to provide an attenuator output signal. At least one of the two or more signal processing units has an associated wearout process and a corresponding wearout budget, wherein a wearout event of the wearout process occurs when a level of a wearout indication signal of the signal processing chain is in a wearout region, and wherein the wearout process is modeled by a wearout event cost associated with a corresponding wearout event. The method comprises obtaining an indication of whether a wearout event of the wearout process has occurred. If the obtained indication shows that a wearout event of the wearout process has occurred, the method comprises updating a wearout accumulation metric of the wearout process by the associated wearout event cost, comparing the wearout accumulation metric of the wearout process with one or more wearout thresholds of the wearout process, and adapting the attenuation parameters of the signal attenuator based on the comparison. The method also comprises controlling the signal attenuator based on the attenuation parameters. Corresponding attenuator control arrangement is also disclosed.
摘要翻译：公开了一种包括两个或多个信号处理单元的信号处理链的衰减器控制方法。两个或更多个信号处理单元之一是信号衰减器，其适于基于一个或多个衰减参数来施加衰减器输入信号的自适应信号衰减以提供衰减器输出信号。两个或更多个信号处理单元中的至少一个具有相关联的耗损过程和相应的耗损预算，其中当信号处理链的耗损指示信号的电平处于耗损区域时，发生损耗过程的损耗事件，并且其中所述损耗过程由与相应的泄漏事件相关联的损耗事件成本来建模。该方法包括获得是否发生了流失过程的损耗事件的指示。如果获得的指示显示已经发生了耗损过程的疲劳事件，则该方法包括通过相关的耗损事件成本来更新损耗过程的耗损累积量度，将损耗过程的损耗积累度量与一个或多个损耗阈值进行比较的麻烦过程，并且基于比较来适应信号衰减器的衰减参数。该方法还包括基于衰减参数控制信号衰减器。还公开了相应的衰减器控制装置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式