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1. 发明申请

US20230053711A1 INTEGRATED CIRCUIT DEVICE DESIGN METHOD AND SYSTEM 有权
公开(公告)号：US20230053711A1
公开(公告)日：2023-02-23
申请号：US17480358
申请日：2021-09-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC NANJING COMPANY, LIMITED
发明人： Qiuyuan WU , Shuang DAI , Chia-Chun LIAO , Meng-Hsuan WU
IPC分类号： G06F30/333 , G06F30/398 , G06F30/392
摘要： A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

2. 发明申请

US20160164530A1 TIME-TO-DIGITAL CONVERTER USING A CONFIGURABLE MULTIPLIER 有权
标题翻译：使用可配置的MULTIPLIER的时间到数字转换器
公开(公告)号：US20160164530A1
公开(公告)日：2016-06-09
申请号：US15045518
申请日：2016-02-17
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Chun LIAO
IPC分类号： H03L7/099 , G04F10/00 , H03L7/085
CPC分类号： H03L7/0991 , G04F10/005 , H03L7/0812 , H03L7/085 , H03L2207/50
摘要： A fractional error correction circuit includes a time-to-digital converter (TDC) configured to detect a phase difference between a reference clock signal and a variable clock signal, and a configurable multiplier coupled with the TDC. The configurable multiplier has a selectable bit size, the selectable bit size being based on a minimum number of bits needed to obtain a reciprocal of a period of the variable clock signal. The TDC is configured to output a fractional error correction value based on the detected phase difference and the reciprocal of the period.
摘要翻译：分数误差校正电路包括被配置为检测参考时钟信号和可变时钟信号之间的相位差的时间数字转换器（TDC）以及与TDC耦合的可配置乘法器。可配置乘法器具有可选择的比特大小，可选择的比特大小基于获得可变时钟信号的周期的倒数所需的最小比特数。 TDC被配置为基于检测到的相位差和周期的倒数输出分数误差校正值。

3. 发明申请

US20230052899A1 METHODS AND APPARATUS OF CHARGE-SHARING LOCKING WITH DIGITAL CONTROLLED OSCILLATORS 有权
公开(公告)号：US20230052899A1
公开(公告)日：2023-02-16
申请号：US17589678
申请日：2022-01-31
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Min-Shueh YUAN , Chao-Chieh LI , Chia-Chun LIAO , Yu-Tso LIN , Wen-Yuan TSAI , Chih-Hsien CHANG
IPC分类号： H03L7/099 , H03L7/107 , H03H17/02
摘要： An integrated circuit device includes a digitally controlled oscillator (DCO), two charge-sharing capacitors, two charge-sharing switches, two pre-charge switches, and two DACs. The DCO has a first inverter and a second inverter. A first charge-sharing capacitor has a first terminal coupled to an input terminal of the first inverter through a first charge-sharing switch. A first DAC has an output terminal coupled to the first terminal of the first charge-sharing capacitor through a first pre-charge switch. A second charge-sharing capacitor has a first terminal coupled to an input terminal or an output terminal of the second inverter through a second charge-sharing switch. A second DAC has an output terminal coupled to the first terminal of the second charge-sharing capacitor through a second pre-charge switch.

4. 发明申请

US20210313328A1 SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME 有权
公开(公告)号：US20210313328A1
公开(公告)日：2021-10-07
申请号：US17353533
申请日：2021-06-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shun-Jang LIAO , Chia-Chun LIAO , Shu-Hui WANG , Shih-Hsun CHANG
IPC分类号： H01L27/092 , H01L21/8234 , H01L27/088 , H01L29/78 , H01L21/28 , H01L21/768 , H01L21/8238 , H01L29/49
摘要： A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.

5. 发明申请

US20160049946A1 ALL DIGITAL PHASE LOCKED LOOP WITH CONFIGURABLE MULTIPLIER HAVING A SELECTABLE BIT SIZE 有权
标题翻译：具有可选位数的可配置乘法器的所有数字相位锁定环
公开(公告)号：US20160049946A1
公开(公告)日：2016-02-18
申请号：US14461098
申请日：2014-08-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Chun LIAO
IPC分类号： H03L7/081 , G04F10/00
CPC分类号： H03L7/0991 , G04F10/005 , H03L7/0812 , H03L7/085 , H03L2207/50
摘要： An all digital phase locked loop comprises a time-to-digital converter and a configurable multiplier. The time-to-digital converter is configured to output a digital code based on a phase difference between a reference clock signal and a variable clock signal. The configurable multiplier is coupled with the time-to-digital converter. The configurable multiplier has a selectable bit size. The selectable bit size is based on a defined minimum number of bits to obtain a reciprocal of a variable clock period. The minimum number of bits is based on a comparison of a first number of bits of a divisor with a second number of bits of a quotient. The time-to-digital converter is configured to multiply the digital code by the reciprocal of the variable clock period to output a fractional error correction value.
摘要翻译：全数字锁相环包括时间 - 数字转换器和可配置乘法器。该时间 - 数字转换器被配置为基于参考时钟信号和可变时钟信号之间的相位差来输出数字码。可配置的乘法器与时间 - 数字转换器耦合。可配置的乘法器具有可选择的位大小。可选择的比特大小基于所定义的最小比特数来获得可变时钟周期的倒数。最小比特数是基于除数的第一比特数与商的第二比特数的比较。时间数字转换器被配置为将数字代码乘以可变时钟周期的倒数以输出分数误差校正值。

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