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1. 发明授权

US11468929B2 Memory circuit and method of operating the same 有权
公开(公告)号：US11468929B2
公开(公告)日：2022-10-11
申请号：US17235297
申请日：2021-04-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. , TSMC CHINA COMPANY, LIMITED
发明人： Yi-Tzu Chen , Ching-Wei Wu , Hau-Tai Shieh , Hung-Jen Liao , Fu-An Wu , He-Zhou Wan , XiuLi Yang
IPC分类号： G11C16/10 , G11C7/22 , G11C7/12 , G11C7/14 , G11C7/10
摘要： A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

2. 发明授权

US11568121B2 FinFET semiconductor device grouping 有权
公开(公告)号：US11568121B2
公开(公告)日：2023-01-31
申请号：US17226428
申请日：2021-04-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Tzu Chen , Hau-Tai Shieh , Che-Ju Yeh
IPC分类号： G06F30/392 , H01L27/092 , G11C11/418 , H01L27/11
摘要： A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

3. 发明申请

US20220199145A1 SUB-WORD LINE DRIVER PLACEMENT FOR MEMORY DEVICE 有权
公开(公告)号：US20220199145A1
公开(公告)日：2022-06-23
申请号：US17687272
申请日：2022-03-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Tzu Chen , Ching-Wei Wu , Hau-Tai Shieh , Hung-Jen Liao
IPC分类号： G11C11/408 , G11C5/02 , G11C11/4093 , G11C5/06
摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

4. 发明授权

US11361810B2 Power mode wake-up for memory on different power domains 有权
公开(公告)号：US11361810B2
公开(公告)日：2022-06-14
申请号：US17103294
申请日：2020-11-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Che-Ju Yeh , Hau-Tai Shieh , Yi-Tzu Chen
IPC分类号： G11C11/4072 , G11C5/06 , G11C5/14 , G11C11/4074
摘要： A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

5. 发明授权

US10354719B2 3D structure for advanced SRAM design to avoid half-selected issue 有权
公开(公告)号：US10354719B2
公开(公告)日：2019-07-16
申请号：US16226956
申请日：2018-12-20
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Yuan Chen , Chien-Yu Huang , Hau-Tai Shieh
IPC分类号： G11C11/418 , G11C5/02 , G11C8/08 , H01L25/065 , G11C11/412 , H01L27/11
摘要： Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.

6. 发明授权

US09501079B2 Data retention voltage clamp 有权
标题翻译：数据保持电压钳
公开(公告)号：US09501079B2
公开(公告)日：2016-11-22
申请号：US14069417
申请日：2013-11-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Yuan Chen , Hau-Tai Shieh
IPC分类号： H01L35/00 , H01L37/00 , H03K3/42 , H03K17/78 , G05F3/24
CPC分类号： G05F3/242
摘要： An apparatus comprises a first signal input, a first transistor, a first line, a first circuit coupled to the first transistor through the first line, a second line coupled to the first line between the first transistor and the first circuit, a second transistor coupled to the first transistor through the second line, a second circuit coupled to the second transistor, the first circuit being a replica of the second circuit, a second signal input, and a third transistor coupled to the second signal input and the second circuit. The apparatus maintains a virtual voltage of the second circuit above a predetermined threshold by a voltage associated with the second line. The voltage associated with the second line is based on a difference between a first current associated with a portion of the first line and a second current associated with another portion of the first line.
摘要翻译：一种装置包括第一信号输入，第一晶体管，第一线，通过第一线耦合到第一晶体管的第一电路，耦合到第一晶体管和第一电路之间的第一线的第二线，耦合到第一晶体管通过第二线耦合到第一晶体管，耦合到第二晶体管的第二电路，第一电路是第二电路的复制品，第二信号输入和耦合到第二信号输入和第二电路的第三晶体管。该装置通过与第二线相关联的电压将第二电路的虚拟电压维持在预定阈值之上。与第二线相关联的电压基于与第一线的一部分相关联的第一电流与与第一线的另一部分相关联的第二电流之间的差异。

7. 发明申请

US20220068355A1 MEMORY CIRCUIT, ELECTRONIC DEVICE HAVING THE MEMORY CIRCUIT, AND METHOD OF OPERATING MEMORY CIRCUIT 有权
公开(公告)号：US20220068355A1
公开(公告)日：2022-03-03
申请号：US17006882
申请日：2020-08-30
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hua-Hsin Yu , Cheng-Hung Lee , Hung-Jen Liao , Hau-Tai Shieh
IPC分类号： G11C11/4091 , G11C11/4074 , G11C11/4076 , G11C11/4099 , G11C7/10
摘要： The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.

8. 发明申请

US20180226412A1 Three-Dimensional Static Random Access Memory Device Structures 审中-公开
公开(公告)号：US20180226412A1
公开(公告)日：2018-08-09
申请号：US15947330
申请日：2018-04-06
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Yu Huang , Chien-Yuan Chen , Hau-Tai Shieh
IPC分类号： H01L27/11 , H01L21/8234 , H01L23/528 , G11C11/419 , G11C11/418
摘要： Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.

9. 发明申请

US20150279450A1 Data-Aware SRAM Systems and Methods Forming Same 审中-公开
标题翻译：数据感知SRAM系统和方法形成相同
公开(公告)号：US20150279450A1
公开(公告)日：2015-10-01
申请号：US14738749
申请日：2015-06-12
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chien-Yuan Chen , Yi-Tzu Chen , Hau-Tai Shieh , Tsung-yung Jonathan Chang
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C11/412 , G11C11/413
摘要： Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.
摘要翻译： SRAM单元的示例性实施例，用于SRAM系统的新的控制单元以及SRAM系统的实施例在此被描述。 SRAM单元被配置为接收具有与第一输入电压信号不同的值的第一输入电压信号和第二输入电压信号，并且保持第一存储值信号和第二存储值信号。控制电路被配置为接收第一输入电压信号和第二输入电压信号，并且由睡眠信号，选择信号和数据输入信号控制，使得控制电路的输出对数据是敏感的输入信号。 SRAM系统包括多个SRAM单元，控制所公开的控制电路，其中SRAM单元分别具有由数据输入信号及其补码信号控制的两个输入电压信号。

10. 发明申请

US20140119104A1 Data-Aware SRAM Systems and Methods Forming Same 审中-公开
标题翻译：数据感知SRAM系统和方法形成相同
公开(公告)号：US20140119104A1
公开(公告)日：2014-05-01
申请号：US14083249
申请日：2013-11-18
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Yuan Chen , Yi-Tzu Chen , Hau-Tai Shieh , Jonathan Tsung-Yung Chang
IPC分类号： G11C11/417
CPC分类号： G11C11/417 , G11C11/412 , G11C11/413
摘要： Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.
摘要翻译： SRAM单元的示例性实施例，用于SRAM系统的新的控制单元以及SRAM系统的实施例在此被描述。 SRAM单元被配置为接收具有与第一输入电压信号不同的值的第一输入电压信号和第二输入电压信号，并且保持第一存储值信号和第二存储值信号。控制电路被配置为接收第一输入电压信号和第二输入电压信号，并且由睡眠信号，选择信号和数据输入信号控制，使得控制电路的输出对数据是敏感的输入信号。 SRAM系统包括多个SRAM单元，控制所公开的控制电路，其中SRAM单元分别具有由数据输入信号及其补码信号控制的两个输入电压信号。

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