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1. 发明授权

US09786780B2 Integrated circuits having source/drain structure 有权
公开(公告)号：US09786780B2
公开(公告)日：2017-10-10
申请号：US14312871
申请日：2014-06-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shih-Hsien Huang , Yi-Fang Pai , Chien-Chang Su
IPC分类号： H01L29/772 , H01L29/41 , H01L29/78 , H01L29/66 , H01L21/02 , H01L29/06 , H01L29/417 , H01L29/165
CPC分类号： H01L29/7833 , H01L21/02636 , H01L29/0692 , H01L29/165 , H01L29/41725 , H01L29/41783 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.

2. 发明授权

US11581425B2 Method for manufacturing semiconductor structure with enlarged volumes of source-drain regions 有权
公开(公告)号：US11581425B2
公开(公告)日：2023-02-14
申请号：US17198683
申请日：2021-03-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Tsung-Hsi Yang , Che-Yu Lin , Yi-Fang Pai , Pei-Ren Jeng , Chii-Horng Li , Yee-Chia Yeo
IPC分类号： H01L29/66 , H01L21/3105 , H01L21/8234 , H01L21/02 , H01L21/8238
摘要： A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.

3. 发明授权

US10734517B2 Integrated circuits having source/drain structure 有权
公开(公告)号：US10734517B2
公开(公告)日：2020-08-04
申请号：US15726530
申请日：2017-10-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shih-Hsien Huang , Yi-Fang Pai , Chien-Chang Su
IPC分类号： H01L29/66 , H01L29/417 , H01L29/78 , H01L21/02 , H01L29/06 , H01L29/165
摘要： The integrated circuit includes a gate structure over a substrate. The integrated circuit further includes a first silicon-containing material structure in a recess adjacent to the gate structure. The first silicon-containing material structure includes a first layer having an uppermost surface below a top surface of the substrate and a bottommost surface in contact with the substrate. The first silicon-containing material structure further includes a second layer over the first layer, wherein an entirety of the second layer is co-planar with or above the top surface of the substrate. A first region of the second layer closer to the gate structure is thicker than a second region of the second layer farther from the gate structure. Thickness is measured in a direction perpendicular to the top surface of the substrate.

4. 发明授权

US09564509B2 Method of fabricating an integrated circuit device 有权
标题翻译：制造集成电路器件的方法
公开(公告)号：US09564509B2
公开(公告)日：2017-02-07
申请号：US14552630
申请日：2014-11-25
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ming-Hsi Yeh , Hsien-Hsin Lin , Ying-Hsueh Chang Chien , Yi-Fang Pai , Chi-Ming Yang , Chin-Hsiang Lin
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L29/665 , H01L21/823807 , H01L21/823814 , H01L21/823864 , Y10S438/976
摘要： A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).
摘要翻译：一种制造集成电路器件的方法包括在衬底的第一区域中形成第一栅极结构，在衬底的第二区域中形成第二栅极结构。该方法包括形成覆盖第一和第二栅极结构的保护层。该方法包括在第二栅极结构上去除保护层的一部分。该方法包括形成与第二栅极结构相邻的特征。该方法还包括在与第二栅极结构相邻的特征的至少一部分上形成间隔物，其中特征将间隔物与邻近第二栅极结构的衬底分开。该方法包括去除保护层的第二部分。去除保护层的第二部分包括在第二栅极结构上形成保护器; 以及使用包含氢氟酸（HF）的化学品进行蚀刻工艺。

5. 发明授权

US09443847B2 Epitaxial formation of source and drain regions 有权
标题翻译：源极和漏极区域的外延形成
公开(公告)号：US09443847B2
公开(公告)日：2016-09-13
申请号：US14675974
申请日：2015-04-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chun Hsiung Tsai , Yi-Fang Pai
IPC分类号： H01L27/088 , H01L29/417 , H01L29/66 , H01L29/08 , H01L29/165 , H01L21/02 , H01L21/8234 , H01L29/06 , H01L29/167 , H01L21/00 , H01L29/78
CPC分类号： H01L27/088 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/823425 , H01L29/0649 , H01L29/0847 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/6659 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： An integrated circuit includes a gate structure disposed over a substrate. The integrated circuit further includes a silicon-containing material structure disposed over a recess adjacent to the gate structure. The silicon-containing material structure includes a first epitaxial layer and a second epitaxial layer. A gate corner of the gate structure is free of dislocation and a corner of the second epitaxial layer away from a surface of the substrate and next to a spacer of the gate structure includes dislocations, wherein the dislocations are away from the gate corner.
摘要翻译：集成电路包括设置在衬底上的栅极结构。集成电路还包括设置在与栅极结构相邻的凹部上的含硅材料结构。含硅材料结构包括第一外延层和第二外延层。栅极结构的栅极角没有位错，并且第二外延层的离开衬底表面的角部和栅极结构的间隔物之间的位置包括位错，其中位错远离栅极拐角。

6. 发明授权

US09412870B2 Device with engineered epitaxial region and methods of making same 有权
标题翻译：具有工程外延区域的器件及其制造方法
公开(公告)号：US09412870B2
公开(公告)日：2016-08-09
申请号：US14833268
申请日：2015-08-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： King-Yuen Wong , Chia-Yu Lu , Chien-Chang Su , Yen-Chun Lin , Yi-Fang Pai , Da-Wen Lin
IPC分类号： H01L21/02 , H01L29/78 , H01L21/8238 , H01L21/8249 , H01L29/66 , H01L29/08 , H01L29/165 , H01L27/06 , H01L29/04 , H01L29/167
CPC分类号： H01L29/0847 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L29/045 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.
摘要翻译：一种器件包括衬底和衬底中的凹部。凹槽具有底部和侧壁。该器件还包括在凹槽的底部上的第一外延层，以及位于第一外延层上方的第二外延层，并且在凹槽的侧壁之上，第二外延层具有与衬底不同的晶格常数。该器件还包括在第二外延层上方的第三外延层并填充凹陷。

7. 发明申请

US20150364602A1 Device with Engineered Epitaxial Region and Methods of Making Same 审中-公开
标题翻译：具有工程外延区域的设备及其制造方法
公开(公告)号：US20150364602A1
公开(公告)日：2015-12-17
申请号：US14833268
申请日：2015-08-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： King-Yuen Wong , Chia-Yu Lu , Chien-Chang Su , Yen-Chun Lin , Yi-Fang Pai , Da-Wen Lin
IPC分类号： H01L29/78 , H01L29/08 , H01L21/02 , H01L29/167 , H01L29/04 , H01L27/06 , H01L29/66 , H01L29/165
CPC分类号： H01L29/0847 , H01L21/02532 , H01L21/0262 , H01L21/823807 , H01L21/823814 , H01L21/8249 , H01L27/0623 , H01L29/045 , H01L29/165 , H01L29/167 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.
摘要翻译：一种器件包括衬底和衬底中的凹部。凹槽具有底部和侧壁。该器件还包括在凹槽的底部上的第一外延层，以及位于第一外延层上方的第二外延层，并且在凹槽的侧壁之上，第二外延层具有与衬底不同的晶格常数。该器件还包括在第二外延层上方的第三外延层并填充凹陷。

8. 发明授权

US11373867B2 Integrated circuits having source/drain structure and method of making 有权
公开(公告)号：US11373867B2
公开(公告)日：2022-06-28
申请号：US16933470
申请日：2020-07-20
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shih-Hsien Huang , Yi-Fang Pai , Chien-Chang Su
IPC分类号： H01L21/20 , H01L29/66 , H01L21/02 , H01L29/06 , H01L29/78 , H01L29/417 , H01L29/165
摘要： An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.

9. 发明授权

US09356150B2 Method for incorporating impurity element in EPI silicon process 有权
公开(公告)号：US09356150B2
公开(公告)日：2016-05-31
申请号：US14833259
申请日：2015-08-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Chang Su , Hsien-Hsin Lin , Tsz-Mei Kwok , Kuan-Yu Chen , Hsueh-Chang Sung , Yi-Fang Pai
IPC分类号： H01L21/8234 , H01L29/78 , H01L21/02 , H01L29/66 , H01L29/06 , H01L29/167
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02573 , H01L21/02576 , H01L21/0262 , H01L29/0653 , H01L29/167 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.

10. 发明申请

US20150364604A1 METHOD FOR INCORPORATING IMPURITY ELEMENT IN EPI SILICON PROCESS 有权
标题翻译：在EPI硅工艺中加入污染元素的方法
公开(公告)号：US20150364604A1
公开(公告)日：2015-12-17
申请号：US14833259
申请日：2015-08-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chien-Chang Su , Hsien-Hsin Lin , Tsz-Mei Kwok , Kuan-Yu Chen , Hsueh-Chang Sung , Yi-Fang Pai
IPC分类号： H01L29/78 , H01L29/66 , H01L29/06 , H01L29/167
CPC分类号： H01L29/7851 , H01L21/02532 , H01L21/02573 , H01L21/02576 , H01L21/0262 , H01L29/0653 , H01L29/167 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.
摘要翻译：本公开提供一种制造半导体器件的方法，该半导体器件包括形成多个翅片，翅片通过隔离结构彼此隔离，在每个翅片的一部分上形成栅极结构; 在栅极结构的侧壁上分别形成间隔物，蚀刻每个鳍片的剩余部分，从而形成凹槽，外延生长硅以填充凹槽，包括掺杂选自锗（Ge），铟（In），和碳（C），并用n型掺杂剂掺杂硅epi。

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