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1. 发明授权

US09754073B2 Layout optimization for integrated circuit design 有权
公开(公告)号：US09754073B2
公开(公告)日：2017-09-05
申请号：US15237286
申请日：2016-08-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50 , G03F7/00
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.

2. 发明授权

US08898600B2 Layout optimization for integrated design 有权
标题翻译：集成设计的布局优化
公开(公告)号：US08898600B2
公开(公告)日：2014-11-25
申请号：US13941941
申请日：2013-07-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F7/0035 , G06F17/5072 , G06F2217/08 , G06F2217/12
摘要： A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
摘要翻译：布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束出区。目标图案应形成相应的主要特征和切割图案。

3. 发明授权

US11620426B2 Automated system and method for circuit design 有权
公开(公告)号：US11620426B2
公开(公告)日：2023-04-04
申请号：US17331825
申请日：2021-05-27
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Shin-Chi Chen , King-Ho Tam , Yu-Ze Lin , Huang-Yu Chen
IPC分类号： G06F30/30 , G06F30/392 , G06F30/327 , G06F30/31 , G06F119/18
摘要： A method in certain embodiments includes using a computer system that includes an EDA tool to generate a layout of an IC device; searching, using a statistical method such as Bayesian optimization process, for one or more input variable parameters, such as the dimensions of the IC device and the dimensions of the voltage areas in the IC device, that results in an optimal characteristic, such as power, performance or area (PPA) of the IC device. A computer system including one or more EDAs configured to perform the method is also disclosed.

4. 发明申请

US20230023165A1 CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING 有权
公开(公告)号：US20230023165A1
公开(公告)日：2023-01-26
申请号：US17937654
申请日：2022-10-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Sheng-Hsiung Chen , Huang-Yu Chen , Chung-Hsing Wang , Jerry Chang Jui Kao
IPC分类号： G06F30/3947 , G06F30/39
摘要： The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

5. 发明申请

US20150095870A1 Methods for Double-Patterning-Compliant Standard Cell Design 审中-公开
标题翻译：双图案化标准单元设计方法
公开(公告)号：US20150095870A1
公开(公告)日：2015-04-02
申请号：US14564934
申请日：2014-12-09
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , H01L23/5286 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
摘要翻译：半导体芯片包括一行单元，其中每个单元包括VDD线和VSS线。单元的所有VDD线连接为单个VDD线，并且单元的所有VSS线都以单个VSS线连接。在单元格行中不存在具有偶数个G0路径的双重图案化完整轨迹，或者在单元行中不存在具有奇数个G0路径的双图案化完整轨迹。

6. 发明申请

US20140282306A1 Layout Optimization for Integrated Design 有权
标题翻译：集成设计布局优化
公开(公告)号：US20140282306A1
公开(公告)日：2014-09-18
申请号：US13941941
申请日：2013-07-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F7/0035 , G06F17/5072 , G06F2217/08 , G06F2217/12
摘要： A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.
摘要翻译：布置目标图案的方法包括：将目标图案的第一特征的末端分配给保留区域，以及定位其他特征，使得目标图案的其它特征的末端在所述保留区域内没有结束出区。目标图案应形成相应的主要特征和切割图案。

7. 发明授权

US09594866B2 Method for checking and fixing double-patterning layout 有权
标题翻译：双图案布局的检查和固定方法
公开(公告)号：US09594866B2
公开(公告)日：2017-03-14
申请号：US13681094
申请日：2012-11-19
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Dio Wang , Ken-Hsien Hsieh , Huang-Yu Chen , Li-Chun Tien , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50 , G03F1/00 , G21K5/00
CPC分类号： G06F17/5081 , G03F1/00 , G06F17/5077 , G06F2217/12 , G21K5/00
摘要： A method includes receiving layout data representing a plurality of patterns. The layout data includes a plurality of layers and spaces identified between adjacent patterns. In at least one layer of the plurality of layers, the adjacent patterns violate a G0-rule. The method further includes determining whether each identified space is a critical G0-space. The identified space is determined to be a critical G0-space if a portion of at least one adjacent pattern that is removed merges two adjacent odd-loops of G0-spaces into a single even loop or G0 spaces or alternatively, if a portion of an adjacent pattern that is removed converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of at least one adjacent pattern and updating a spacing of a layer that is adjacent to the layers within the adjacent pattern that violate the G0-rule.
摘要翻译：一种方法包括接收表示多个图案的布局数据。布局数据包括在相邻图案之间标识的多个层和空间。在多层中的至少一层中，相邻的图案违反了G0规则。该方法还包括确定每个所识别的空间是否是关键的G0空间。如果去除的至少一个相邻图案的一部分将G0空间的两个相邻奇数循环合并成单个偶数循环或G0空间，则所识别的空间被确定为关键G0空间，或者如果一部分被删除的相邻图案将一个奇数循环的G0空间转换成非循环的G0空格。该方法还包括接收至少一个相邻图案的修改，并且更新与相邻图案中违反G0规则的层相邻的层的间隔。

8. 发明申请

US20160350473A1 Layout Optimization for Integrated Circuit Design 有权
标题翻译：集成电路设计布局优化
公开(公告)号：US20160350473A1
公开(公告)日：2016-12-01
申请号：US15237286
申请日：2016-08-15
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
摘要翻译：一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或在检查期间发现第二个约束。

9. 发明授权

US09471742B2 Method for displaying timing information of an integrated circuit floorplan in real time 有权
标题翻译：实时显示集成电路平面布置图的定时信息的方法
公开(公告)号：US09471742B2
公开(公告)日：2016-10-18
申请号：US14523176
申请日：2014-10-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yi-Lin Chuang , Huang-Yu Chen , Yun-Han Lee
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5031 , G06F17/5068 , G06F17/5072 , G06F2217/06 , G06F2217/84
摘要： A method includes (a) generating timing information of an integrated circuit (IC) floorplan by a processing unit, (b) displaying on a display device a representation of the IC floorplan according to the timing information, (c) receiving user input via an input device, the user input associated with an IC macro of the IC floorplan, (d) updating the timing information associated with the IC macro to generated updated timing information according to the user input, and (e) altering display of the representation according to the updated timing information.
摘要翻译：一种方法包括：（a）由处理单元生成集成电路（IC）平面布置图的定时信息，（b）根据定时信息在显示设备上显示IC楼层布置图的表示，（c）经由输入设备，与IC平面布置图的IC宏相关联的用户输入，（d）根据用户输入更新与IC宏关联的定时信息以生成更新的定时信息，以及（e）根据用户输入更改表示的显示更新的定时信息。

10. 发明申请

US20150199469A1 LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN 有权
标题翻译：集成电路设计的布局优化
公开(公告)号：US20150199469A1
公开(公告)日：2015-07-16
申请号：US14598773
申请日：2015-01-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Huang-Yu Chen , Yuan-Te Hou , Yu-Hsiang Kao , Ken-Hsien Hsieh , Ru-Gun Liu , Lee-Chung Lu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F7/0035 , G06F17/5068 , G06F17/5072 , G06F2217/08 , G06F2217/12 , Y02P90/265
摘要： A method includes receiving a target pattern that is defined by a main pattern, a first cut pattern, and a second cut pattern, with a computing system, checking the target pattern for compliance with a first constraint, the first constraint associated with the first cut pattern, with the computing system, checking the target pattern for compliance with a second constraint, the second constraint associated with the second cut pattern, and with the computing system, modifying the pattern in response to determining that a violation of either the first constraint or the second constraint is found during the checking.
摘要翻译：一种方法包括用计算系统接收由主图案，第一切割图案和第二切割图案定义的目标图案，检查目标图案是否符合第一约束条件，与第一切割相关联的第一约束模式，与所述计算系统一起，检查所述目标模式是否符合第二约束，所述第二约束与所述第二剪切模式相关联，并且与所述计算系统一起修改所述模式以响应于确定违反所述第一约束或在检查期间发现第二个约束。

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