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1. 发明申请

US20170053890A1 ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS 有权
标题翻译：静电放电保护装置和工艺
公开(公告)号：US20170053890A1
公开(公告)日：2017-02-23
申请号：US15345134
申请日：2016-11-07
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Wen-Chien CHANG , Hsiang-Tai LU , Dai-Jang CHEN , Chih-Hsien LIN
IPC分类号： H01L23/00 , H01L25/065 , H01L23/498 , H01L25/00 , H01L23/60
CPC分类号： H01L24/75 , H01L21/67207 , H01L23/49827 , H01L23/60 , H01L24/03 , H01L24/04 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/0361 , H01L2224/0362 , H01L2224/038 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/0558 , H01L2224/05655 , H01L2224/05666 , H01L2224/1146 , H01L2224/11849 , H01L2224/13005 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/75101 , H01L2224/752 , H01L2224/81009 , H01L2225/06513 , H01L2225/06541 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/15788 , H01L2924/30205 , H05F3/02 , Y10T29/52 , H01L2924/00 , H01L2924/014 , H01L2924/00014 , H01L2924/207 , H01L2924/01029 , H01L2924/01047
摘要： In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
摘要翻译：在一个过程中，在衬底中形成至少一个电路元件。导电层形成在衬底上并与至少一个电路元件电接触。静电电荷经由导电层从基板排出。

2. 发明公开

US20240094282A1 CIRCUIT TEST STRUCTURE AND METHOD OF USING 审中-公开
公开(公告)号：US20240094282A1
公开(公告)日：2024-03-21
申请号：US18517260
申请日：2023-11-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ching-Fang CHEN , Hsiang-Tai LU , Chih-Hsien LIN
IPC分类号： G01R31/28 , H01L21/66 , H01L23/00 , H01L23/12 , H01L23/498
CPC分类号： G01R31/2856 , G01R31/2886 , H01L22/34 , H01L23/12 , H01L23/49827 , H01L24/16 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227
摘要： A circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line.

3. 发明申请

US20170292991A1 CIRCUIT TEST STRUCTURE 审中-公开
公开(公告)号：US20170292991A1
公开(公告)日：2017-10-12
申请号：US15633136
申请日：2017-06-26
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ching-Fang CHEN , Hsiang-Tai LU , Chih-Hsien LIN
IPC分类号： G01R31/28 , H01L23/498 , H01L23/00 , H01L21/66
CPC分类号： G01R31/2856 , G01R31/2886 , H01L22/34 , H01L23/12 , H01L23/49827 , H01L24/16 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01047
摘要： A circuit test structure includes: a chip including a conductive line which traces a perimeter of the chip; an interposer electrically connected to the chip; and a Kelvin test structure including: at least three electrical connections to the conductive line; and a testing site. The Kelvin test structure is configured to electrically connect the testing site to the conductive line.

4. 发明申请

US20190257880A1 CIRCUIT TEST STRUCTURE 审中-公开
公开(公告)号：US20190257880A1
公开(公告)日：2019-08-22
申请号：US16401850
申请日：2019-05-02
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ching-Fang CHEN , Hsiang-Tai LU , Chih-Hsien LIN
IPC分类号： G01R31/28 , H01L23/498 , H01L23/12 , H01L21/66 , H01L23/00
摘要： A circuit test structure including an interposer for electrically connection to a chip, wherein the interposer includes a conductive line, and the conductive line traces a perimeter of the interposer. The circuit test structure further includes at least three electrical connections to the conductive line. The circuit test structure further includes a testing site. The circuit test structure further includes a through substrate via (TSV) connecting the testing site to the conductive line.

5. 发明申请

US20140087548A1 METHOD OF SHIELDING THROUGH SILICON VIAS IN A PASSIVE INTERPOSER 有权
标题翻译：通过无源插座中的硅离子进行屏蔽的方法
公开(公告)号：US20140087548A1
公开(公告)日：2014-03-27
申请号：US14094847
申请日：2013-12-03
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Hsiang-Tai LU , Chih-Hsien LIN , Meng-Lin CHUNG
IPC分类号： H01L21/265 , H01L23/552
CPC分类号： H01L21/265 , H01L21/76802 , H01L23/147 , H01L23/49827 , H01L23/5225 , H01L23/552 , H01L2224/16
摘要： A method of shielding through silicon vias (TSVs) in a passive interposer includes doping a substrate with positive ions, and implanting positive ions in an upper portion of the substrate, such that the substrate has at least a p-doped portion and a heavily p-doped upper portion. The method further includes forming an interlayer dielectric (ILD) above the heavily p-doped upper portion. The method further includes forming a plurality of through silicon vias (TSVs) through the ILD and the substrate, such that the passive interposer is configured to electrically couple at least one structure above and below the passive interposer. The method further includes forming, between pairs of TSVs of the plurality of TSVs, a plurality of shielding lines through the interlayer dielectric, the shielding lines configured to electrically couple the heavily p-doped upper portion of the substrate and at least one interconnect structure above the ILD.
摘要翻译：在无源插入器中通过硅通孔（TSV）屏蔽的方法包括用正离子掺杂衬底，并在衬底的上部注入正离子，使得衬底至少具有p掺杂部分和大量p 掺杂上部。该方法还包括在高p掺杂的上部部分上形成层间电介质（ILD）。该方法还包括通过ILD和衬底形成多个穿通硅通孔（TSV），使得被动中插入口被配置为电耦合无源插入器的上方和下方的至少一个结构。所述方法还包括在所述多个TSV的TSV对之间形成穿过所述层间电介质的多条屏蔽线，所述屏蔽线被配置为电耦合所述衬底的所述p掺杂的高部分和至少一个互连结构 ILD。

6. 发明公开

US20240047384A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240047384A1
公开(公告)日：2024-02-08
申请号：US18109116
申请日：2023-02-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chi-Hui LAI , Yang-Che CHEN , Hsiang-Tai LU , Wei-Ray LIN
IPC分类号： H01L23/58 , H01L23/528 , H01L21/78
CPC分类号： H01L23/585 , H01L23/528 , H01L21/78
摘要： A semiconductor device includes a first circuit area disposed over a substrate and enclosed by a first seal ring structure, a second circuit area disposed over the substrate and enclosed by a second seal ring structure, an internal scribe line disposed between the first circuit area and the second circuit area, and connecting seal structures connecting the first seal ring structure and the second seal ring structures such that a part of the first seal ring structure, a part of the second seal ring structure and the connecting seal structures enclose the internal scribe line.

7. 发明申请

US20210231730A1 CIRCUIT TEST STRUCTURE AND METHOD OF USING 有权
公开(公告)号：US20210231730A1
公开(公告)日：2021-07-29
申请号：US17229269
申请日：2021-04-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ching-Fang CHEN , Hsiang-Tai LU , Chih-Hsien LIN
IPC分类号： G01R31/28 , H01L23/00 , H01L23/12 , H01L23/498 , H01L21/66
摘要： A circuit test structure includes an interposer for electrically connecting to a chip, wherein the interposer includes a conductive line, and the conductive line extends along at least two side of the interposer. The circuit test structure further includes a plurality of electrical connections to the conductive line. The circuit test structure further includes a testing site electrically connected to the conductive line, wherein the testing site is on an opposite surface of the interposer from the plurality of electrical connections.

8. 发明申请

US20150234004A1 METHOD OF TESTING A THREE-DIMENSIONAL INTEGRATED CIRCUIT 有权
标题翻译：测量三维集成电路的方法
公开(公告)号：US20150234004A1
公开(公告)日：2015-08-20
申请号：US14700822
申请日：2015-04-30
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ching-Fang CHEN , Hsiang-Tai LU , Chih-Hsien LIN
IPC分类号： G01R31/28
CPC分类号： G01R31/2886 , G01R31/2856 , H01L22/34 , H01L23/12 , H01L23/49827 , H01L24/16 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/16225 , H01L2224/16227 , H01L2924/00014 , H01L2924/01047
摘要： A method of testing a three-dimensional integrated circuit (3DIC) includes applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer substantially parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors. The method further includes measuring a current responsive to the applied voltage. The method further includes determining an integrity of the 3DIC based on the measured current.
摘要翻译：一种测试三维集成电路（3DIC）的方法包括通过至少一个测试元件和至少一个导电线施加电压，其中所述至少一个导电线跟踪顶部芯片或者至少一个的至少一个的周边插入器基本上平行于至少一个顶部芯片或插入器的外边缘，并且所述至少一个导电线被配置为电连接多个导电连接器。该方法还包括测量响应于所施加的电压的电流。该方法还包括基于测量的电流来确定3DIC的完整性。

9. 发明申请

US20150079735A1 ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS 有权
标题翻译：静电放电保护装置和工艺
公开(公告)号：US20150079735A1
公开(公告)日：2015-03-19
申请号：US14026060
申请日：2013-09-13
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Wen-Chien CHANG , Hsiang-Tai LU , Dai-Jang CHEN , Chih-Hsien LIN
IPC分类号： H05F3/02 , H01L23/00 , H01L21/283
CPC分类号： H01L24/75 , H01L21/67207 , H01L23/49827 , H01L23/60 , H01L24/03 , H01L24/04 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0346 , H01L2224/0361 , H01L2224/0362 , H01L2224/038 , H01L2224/03912 , H01L2224/0401 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05572 , H01L2224/0558 , H01L2224/05655 , H01L2224/05666 , H01L2224/1146 , H01L2224/11849 , H01L2224/13005 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/75101 , H01L2224/752 , H01L2224/81009 , H01L2225/06513 , H01L2225/06541 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/15788 , H01L2924/30205 , H05F3/02 , Y10T29/52 , H01L2924/00 , H01L2924/014 , H01L2924/00014 , H01L2924/207 , H01L2924/01029 , H01L2924/01047
摘要： In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer.
摘要翻译：在一个过程中，在衬底中形成至少一个电路元件。导电层形成在衬底上并与至少一个电路元件电接触。静电电荷经由导电层从基板排出。

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