专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11901286B2 Diagonal via pattern and method 有权
公开(公告)号：US11901286B2
公开(公告)日：2024-02-13
申请号：US17334320
申请日：2021-05-28
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Shih-Wei Peng , Chih-Min Hsiao , Ching-Hsu Chang , Jiann-Tyng Tzeng
IPC分类号： H01L23/00 , H01L23/522 , G06F30/392 , G06F30/394 , G03F1/42 , H01L23/528 , G06F30/31 , H01L21/768
CPC分类号： H01L23/5226 , G03F1/42 , G06F30/392 , G06F30/394 , G06F30/31 , H01L21/76816 , H01L21/76877 , H01L23/528
摘要： A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

2. 发明授权

US09298083B2 Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof 有权
标题翻译：极紫外光（EUV）光掩模及其制造方法
公开(公告)号：US09298083B2
公开(公告)日：2016-03-29
申请号：US14279577
申请日：2014-05-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ching-Hsu Chang , Hung-Chun Wang , Boren Luo , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G03F1/24 , G03F1/58
CPC分类号： G03F1/58 , G03F1/24
摘要： An extreme ultraviolet photomask comprises a reflective layer over a substrate, a capping layer over the reflective layer, a hard mask layer over the capping layer, and an absorber. The absorber is in the hard mask layer, the capping layer and the reflective layer.
摘要翻译：极紫外光掩模包括在衬底上的反射层，反射层上的覆盖层，覆盖层上的硬掩模层和吸收体。吸收体位于硬掩模层，封盖层和反射层中。

3. 发明授权

US10360339B2 Method for integrated circuit manufacturing 有权
公开(公告)号：US10360339B2
公开(公告)日：2019-07-23
申请号：US15043961
申请日：2016-02-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan Wu , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
IPC分类号： G06F17/50 , G03F1/00 , G03F7/20 , G03F1/36 , H01L27/02
摘要： Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.

4. 发明申请

US20160327854A1 Enhanced EUV Lithography System 有权
标题翻译：增强型EUV光刻系统
公开(公告)号：US20160327854A1
公开(公告)日：2016-11-10
申请号：US15211229
申请日：2016-07-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Hsu Chang , Nian-Fuh Cheng , Chih-Shiang Chou , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G03F1/22 , G03F7/20
CPC分类号： G03F1/22 , G03F1/70 , G03F7/70066 , G03F7/70283 , G03F7/70433
摘要： The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.
摘要翻译：本公开提供了一种半导体光刻系统。光刻系统包括投影光学部件。投影光学部件包括弯曲孔。光刻系统包括位于投影光学部件上的光掩模。光掩模包含多个细长半导体图案。半导体图案各自指向基本上垂直于投影光学部件的弯曲孔径的方向。本公开还提供了一种方法。该方法包括接收半导体器件的设计布局。设计布局包含多个沿给定方向定向的半导体图案。该方法包括将设计布局转换为蒙版布局。作为其各自位置的函数，掩模布局中的半导体图案被定向在多个不同的方向上。

5. 发明申请

US20150331333A1 ENHANCED EUV LITHOGRAPHY SYSTEM 有权
标题翻译：增强的EUV光刻系统
公开(公告)号：US20150331333A1
公开(公告)日：2015-11-19
申请号：US14807999
申请日：2015-07-24
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ching-Hsu Chang , Nian-Fuh Cheng , Chih-Shiang Chou , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G03F7/20 , G03F1/22
CPC分类号： G03F1/22 , G03F1/70 , G03F7/70066 , G03F7/70283 , G03F7/70433
摘要： The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.
摘要翻译：本公开提供了一种半导体光刻系统。光刻系统包括投影光学部件。投影光学部件包括弯曲孔。光刻系统包括位于投影光学部件上的光掩模。光掩模包含多个细长半导体图案。半导体图案各自指向基本上垂直于投影光学部件的弯曲孔径的方向。本公开还提供了一种方法。该方法包括接收半导体器件的设计布局。设计布局包含多个沿给定方向定向的半导体图案。该方法包括将设计布局转换为蒙版布局。作为其各自位置的函数，掩模布局中的半导体图案被定向在多个不同的方向上。

6. 发明授权

US09880460B2 Enhanced EUV lithography system 有权
公开(公告)号：US09880460B2
公开(公告)日：2018-01-30
申请号：US15211229
申请日：2016-07-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ching-Hsu Chang , Nian-Fuh Cheng , Chih-Shiang Chou , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G03F1/22 , G03F1/70 , G03F7/20
CPC分类号： G03F1/22 , G03F1/70 , G03F7/70066 , G03F7/70283 , G03F7/70433
摘要： The present disclosure provides a semiconductor lithography system. The lithography system includes a projection optics component. The projection optics component includes a curved aperture. The lithography system includes a photo mask positioned over the projection optics component. The photo mask contains a plurality of elongate semiconductor patterns. The semiconductor patterns each point in a direction substantially perpendicular to the curved aperture of the projection optics component. The present disclosure also provides a method. The method includes receiving a design layout for a semiconductor device. The design layout contains a plurality of semiconductor patterns each oriented in a given direction. The method includes transforming the design layout into a mask layout. The semiconductor patterns in the mask layout are oriented in a plurality of different directions as a function of their respective location.

7. 发明申请

US20160162627A1 Method for Integrated Circuit Manufacturing 审中-公开
标题翻译：集成电路制造方法
公开(公告)号：US20160162627A1
公开(公告)日：2016-06-09
申请号：US15043961
申请日：2016-02-15
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan WU , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
IPC分类号： G06F17/50 , G03F1/36
CPC分类号： G06F17/5081 , G03F1/36 , G03F7/70441 , G06F17/5068 , G06F2217/12 , H01L27/0207
摘要： Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.
摘要翻译：提供了一种集成电路（IC）制造方法。该方法包括接收IC设计布局，其中IC设计布局包括多个IC区域，并且每个IC区域包括初始IC图案。该方法还包括对第一IC区域执行校正处理，从而修改第一IC区域中的初始IC图案，以产生第一IC区域中的第一校正IC图案，其中校正处理包括位置效果校正。该方法还包括用第一校正IC图案替换第二IC区域中的初始IC图案。

8. 发明申请

US20150310158A1 Method for Integrated Circuit Manufacturing 有权
标题翻译：集成电路制造方法
公开(公告)号：US20150310158A1
公开(公告)日：2015-10-29
申请号：US14293050
申请日：2014-06-02
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Chun Wang , Ching-Hsu Chang , Feng-Ju Chang , Chun-Hung Wu , Ping-Chieh Wu , Wen-Hao Liu , Ming-Hsuan Wu , Feng-Lung Lin , Cheng Kun Tsai , Wen-Chun Huang , Ru-Gun Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F7/70441
摘要： Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.
摘要翻译：提供了一种集成电路（IC）制造方法。该方法包括接收IC的设计布局，其中设计布局包括多个不重叠的IC区域，并且每个IC区域包括相同的初始IC图案。该方法还包括基于位置效应分析将IC区域分成多个组，使得相应组中的所有IC区域具有基本上相同的位置效果。该方法还包括使用包括位置效应的校正模型对每个组中的一个IC区域进行校正; 并将校正后的IC区域复制到各组的其他IC区域。该方法还包括将经修正的IC设计布局存储在有形的计算机可读介质中以供另外的IC处理级使用。

9. 发明授权

US10747938B2 Method for integrated circuit manufacturing 有权
公开(公告)号：US10747938B2
公开(公告)日：2020-08-18
申请号：US16516853
申请日：2019-07-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan Wu , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
IPC分类号： G06F17/50 , G06F30/398 , G03F7/20 , G03F1/36 , H01L27/02 , G06F30/39 , G06F119/18
摘要： An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.

10. 发明申请

US20190340330A1 Method for Integrated Circuit Manufacturing 审中-公开
公开(公告)号：US20190340330A1
公开(公告)日：2019-11-07
申请号：US16516853
申请日：2019-07-19
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Hung-Chun Wang , Ching-Hsu Chang , Chun-Hung Wu , Cheng Kun Tsai , Feng-Ju Chang , Feng-Lung Lin , Ming-Hsuan WU , Ping-Chieh Wu , Ru-Gun Liu , Wen-Chun Huang , Wen-Hao Liu
IPC分类号： G06F17/50 , G03F7/20 , G03F1/36
摘要： An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式