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1. 发明授权

US11004858B2 Semiconductor device and manufacturing method thereof 有权
公开(公告)号：US11004858B2
公开(公告)日：2021-05-11
申请号：US16370736
申请日：2019-03-29
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Tsun-Kai Tsao , Hung-Ling Shih , Po-Wei Liu , Shun-Shing Yang , Wen-Tuo Huang , Yong-Shiuan Tsair , S. K. Yang
IPC分类号： H01L27/11529 , H01L21/28 , H01L29/423 , H01L27/11521 , H01L21/3105
摘要： A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

2. 发明授权

US09997524B2 Semiconductor memory device and manufacturing method thereof 有权
公开(公告)号：US09997524B2
公开(公告)日：2018-06-12
申请号：US15272067
申请日：2016-09-21
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Hung-Ling Shih , Chieh-Fei Chiu , Po-Wei Liu , Tsun-Kai Tsao , Wen-Tuo Huang , Yu-Ling Hsu , Yong-Shiuan Tsair
IPC分类号： H01L29/788 , H01L27/11521
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42324
摘要： A memory device includes a substrate. An insulation layer is disposed in a recess in the substrate. A first gate structure is disposed over the substrate and the insulation layer. A first etch stop layer is disposed over the first gate structure. A first oxide layer is disposed over the first etch stop layer. A second etch stop layer is disposed over the first oxide layer. A first contact material is surrounded by and in contact with the first gate structure, first etch stop layer, second etch stop layer, and first oxide layer.

3. 发明授权

US09917003B2 Trench liner passivation for dark current improvement 有权
公开(公告)号：US09917003B2
公开(公告)日：2018-03-13
申请号：US13930189
申请日：2013-06-28
申请人： Taiwan Semiconductor Manufacturing Co., LTD.
发明人： Cheng-Hsien Chou , Hung-Ling Shih , Tsun-Kai Tsao , Ming-Huei Shen , Kuo-Hwa Tzeng , Yeur-Luen Tu
IPC分类号： H01L21/762 , H01L21/02
CPC分类号： H01L21/76224 , H01L21/0217 , H01L21/022 , H01L21/02211
摘要： A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.

4. 发明申请

US20160035736A1 High Endurance Non-Volatile Memory Cell 有权
标题翻译：高耐久性非易失性记忆体
公开(公告)号：US20160035736A1
公开(公告)日：2016-02-04
申请号：US14445697
申请日：2014-07-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hung-Ling Shih , Yong-Shiuan Tsair , Tsun-Kai Tsao , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu
IPC分类号： H01L27/115 , H01L29/06 , H01L29/49 , H01L21/321 , H01L21/027 , H01L21/28 , H01L21/762 , H01L29/423 , H01L29/51
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L29/0649 , H01L29/42324 , H01L29/4916 , H01L29/513 , H01L29/518 , H01L29/66825
摘要： The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.
摘要翻译：本公开涉及非易失性存储器单元结构以及相关联的方法。非易失性存储单元包括两个彼此间隔开的晶体管，浮置栅极通过浮栅连接在一起。在操作期间，非易失性存储单元被编程并从一个第一晶体管擦除并从另一个第二晶体管读取。由于两个晶体管的浮置栅极连接在一起并与其他环境层绝缘，所以可以从第一晶体管控制存储的电荷并影响第二晶体管的阈值。

5. 发明申请

US20160013195A1 METHOD TO IMPROVE MEMORY CELL ERASURE 有权
标题翻译：改善记忆细胞损伤的方法
公开(公告)号：US20160013195A1
公开(公告)日：2016-01-14
申请号：US14326562
申请日：2014-07-09
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tsun-Kai Tsao , Yong-Shiuan Tsair , Hung-Ling Shih , Po-Wei Liu , Wen-Tuo Huang
IPC分类号： H01L27/115 , H01L29/788 , H01L21/3213 , H01L21/28 , H01L21/768 , H01L23/528 , H01L29/423 , H01L29/66
CPC分类号： H01L23/528 , H01L21/28273 , H01L21/32137 , H01L27/11524 , H01L29/42328 , H01L29/6656 , H01L29/66825 , H01L29/7881 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate that includes a first source/drain region and a second source/drain region. The semiconductor structure further includes an erase gate located over the first source/drain region, and a word line and a floating gate located over the semiconductor substrate between the first and second source/drain regions. The floating gate is arranged between the word line and the erase gate. Further, the floating gate includes a pair of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively, of the floating gate. A method of manufacturing the semiconductor structure using a high selectively etch recipe, such as an etch recipe comprised of primarily hydrogen bromide (HBr) and oxygen, is also provided.
摘要翻译：提供了分离栅闪存单元的半导体结构。半导体结构包括包括第一源极/漏极区域和第二源极/漏极区域的半导体衬底。半导体结构还包括位于第一源极/漏极区域上方的擦除栅极以及位于第一和第二源极/漏极区域之间的位于半导体衬底之上的字线和浮置栅极。浮栅位于字线与擦除栅之间。此外，浮动栅极包括从浮动栅极的顶表面垂直向上延伸并且分别布置在浮动栅极的相对侧上的一对突起。还提供了使用高选择性蚀刻配方制造半导体结构的方法，例如主要由溴化氢（HBr）和氧组成的蚀刻配方。

6. 发明授权

US09147710B2 Photodiode gate dielectric protection layer 有权
标题翻译：光电二极管介质保护层
公开(公告)号：US09147710B2
公开(公告)日：2015-09-29
申请号：US13948217
申请日：2013-07-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Cheng-Hsien Chou , Wen-I Hsu , Tsun-Kai Tsao , Chih-Yu Lai , Jiech-Fun Lu , Yeur-Luen Tu
IPC分类号： H01L31/062 , H01L31/113 , H01L27/146 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/14636 , H01L27/14643 , H01L27/14689 , H01L31/18
摘要： The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.
摘要翻译：本公开涉及一种方法，本公开涉及一种有源像素传感器，其具有栅极介电保护层，其在制造期间减小对下面的栅极介电层的损伤，以及相关联的形成方法。在一些实施例中，有源像素传感器具有设置在半导体衬底内的光电检测器。具有第一栅极结构的转移晶体管位于设置在半导体衬底之上的第一栅极电介质层上。具有第二栅极结构的复位晶体管位于第一栅极介电层上。在第一栅极结构和第二栅极结构之间并且在光电检测器上方的位置处，在栅极氧化物上设置栅极介电保护层。栅极介质保护层在制造有源像素传感器期间保护第一栅极介电层免受蚀刻过程。

7. 发明授权

US10312278B2 Front side illuminated image sensor device structure and method for forming the same 有权
公开(公告)号：US10312278B2
公开(公告)日：2019-06-04
申请号：US15644022
申请日：2017-07-07
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tsun-Kai Tsao , Shih-Pei Chou , Jiech-Fun Lu
IPC分类号： H01L27/146
摘要： An FSI image sensor device structure is provided. The FSI image sensor device structure includes a pixel region formed in a substrate and a storage region formed in the substrate and adjacent to the pixel region. The FSI image sensor device structure includes a storage gate structure formed over the storage region, and the storage gate structure includes a top surface and sidewall surfaces. The FSI image sensor device structure includes a metal shield structure formed on the storage gate structure, and the top surface and the sidewall surfaces of the storage gate structure are covered by the metal shield structure.

8. 发明授权

US09252150B1 High endurance non-volatile memory cell 有权
标题翻译：高耐久性非易失性存储单元
公开(公告)号：US09252150B1
公开(公告)日：2016-02-02
申请号：US14445697
申请日：2014-07-29
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hung-Ling Shih , Yong-Shiuan Tsair , Tsun-Kai Tsao , Po-Wei Liu , Wen-Tuo Huang , Yu-Ling Hsu
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/06 , H01L29/49 , H01L29/51 , H01L21/027 , H01L21/28 , H01L21/762 , H01L21/321
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76224 , H01L29/0649 , H01L29/42324 , H01L29/4916 , H01L29/513 , H01L29/518 , H01L29/66825
摘要： The present disclosure relates to a non-volatile memory cell structure, and an associated method. A non-volatile memory cell includes two transistors spaced apart from one another with floating gates connected together by a floating gate bridge. During the operation, the non-volatile memory cell is programmed and erased from one first transistor and read from the other second transistor. Since the floating gates of the two transistors are connected together and insulated from other ambient layers, stored charges can be controlled from the first transistor and affect a threshold of the second transistor.
摘要翻译：本公开涉及非易失性存储器单元结构以及相关联的方法。非易失性存储单元包括两个彼此间隔开的晶体管，浮置栅极通过浮栅连接在一起。在操作期间，非易失性存储单元被编程并从一个第一晶体管擦除并从另一个第二晶体管读取。由于两个晶体管的浮置栅极连接在一起并与其他环境层绝缘，所以可以从第一晶体管控制存储的电荷并影响第二晶体管的阈值。

9. 发明申请

US20160020243A1 PHOTODIODE GATE DIELECTRIC PROTECTION LAYER 有权
公开(公告)号：US20160020243A1
公开(公告)日：2016-01-21
申请号：US14867070
申请日：2015-09-28
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Cheng-Hsien Chou , Wen-I Hsu , Tsun-Kai Tsao , Chih-Yu Lai , Jiech-Fun Lu , Yeur-Luen Tu
IPC分类号： H01L27/146
CPC分类号： H01L27/14614 , H01L27/14636 , H01L27/14643 , H01L27/14689 , H01L31/18
摘要： The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.

10. 发明申请

US20150028402A1 PHOTODIODE GATE DIELECTRIC PROTECTION LAYER 有权
标题翻译：光电栅介质保护层
公开(公告)号：US20150028402A1
公开(公告)日：2015-01-29
申请号：US13948217
申请日：2013-07-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Cheng-Hsien Chou , Wen-I Hsu , Tsun-Kai Tsao , Chih-Yu Lai , Jiech-Fun Lu , Yeur-Luen Tu
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14614 , H01L27/14636 , H01L27/14643 , H01L27/14689 , H01L31/18
摘要： The present disclosure relates to a method the present disclosure relates to an active pixel sensor having a gate dielectric protection layer that reduces damage to an underlying gate dielectric layer during fabrication, and an associated method of formation. In some embodiments, the active pixel sensor has a photodetector disposed within a semiconductor substrate. A transfer transistor having a first gate structure is located on a first gate dielectric layer disposed above the semiconductor substrate. A reset transistor having a second gate structure is located on the first gate dielectric layer. A gate dielectric protection layer is disposed onto the gate oxide at a position extending between the first gate structure and the second gate structure and over the photodetector. The gate dielectric protection layer protects the first gate dielectric layer from etching procedures during fabrication of the active pixel sensor.
摘要翻译：本公开涉及一种方法，本公开涉及一种有源像素传感器，其具有栅极介电保护层，其在制造期间减小对下面的栅极介电层的损坏，以及相关联的形成方法。在一些实施例中，有源像素传感器具有设置在半导体衬底内的光电检测器。具有第一栅极结构的转移晶体管位于设置在半导体衬底之上的第一栅极电介质层上。具有第二栅极结构的复位晶体管位于第一栅极介电层上。在第一栅极结构和第二栅极结构之间并且在光电检测器上方的位置处，在栅极氧化物上设置栅极介电保护层。栅极介质保护层在制造有源像素传感器期间保护第一栅极介电层免受蚀刻过程。

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