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1. 发明授权

US09281273B1 Designed-based interconnect structure in semiconductor structure 有权
标题翻译：半导体结构中基于设计的互连结构
公开(公告)号：US09281273B1
公开(公告)日：2016-03-08
申请号：US14476349
申请日：2014-09-03
申请人： Taiwan Semiconductor Manufacturing Co., Ltd
发明人： Chih-Liang Chen , Chih-Ming Lai , Yung-Sung Yen , Kam-Tou Sio , Tsong-Hua Ou , Chun-Kuang Chen , Ru-Gun Liu , Shu-Hui Sung , Charles Chew-Yuen Young
IPC分类号： H01L27/118 , H01L23/528 , H01L23/522
CPC分类号： H01L23/528 , H01L23/5226 , H01L27/0207 , H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation: 0.2 ⁢ ⁢ P gate ⁢ ⁢ min + 0.35 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min - 20 0.2 ⁢ ⁢ L gate ⁢ ⁢ min + 0.8 ⁢ ⁢ H gate ⁢ ⁢ min - 5 × 0.3 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures. Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.
摘要翻译：提供半导体结构。半导体结构包括沿着形成在衬底上的第一方向延伸的多个栅极结构以及与衬底上的栅极结构相邻形成的触点。半导体结构还包括形成在栅极结构上的多个金属层。此外，一些金属层包括在第一方向上延伸的金属线，并且一些金属层包括沿基本上垂直于第一方向的第二方向延伸的金属线。此外，门结构遵循以下公式：0.2⁢P gate⁢⁢min⁢⁢⁢⁢⁢⁢⁢min min min min⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢⁢ H门槛最小 - 5×0.3⁢L门⁢最小+ 0.3⁢H门⁢最小+ 5 38≤0.32 P门min是门结构的栅间距中的最小值。 Lgate min是门结构的栅极长度之间的最小值。 Hgate min是门结构栅极高度的最小值。

2. 发明授权

US11581314B2 Integrated circuits and manufacturing methods thereof 有权
公开(公告)号：US11581314B2
公开(公告)日：2023-02-14
申请号：US16723939
申请日：2019-12-20
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Ali Keshavarzi , Ta-Pen Guo , Shu-Hui Sung , Hsiang-Jen Tseng , Shyue-Shyh Lin , Lee-Chung Lu , Chung-Cheng Wu , Li-Chun Tien , Jung-Chan Yang , Ting Yu Chen , Min Cao , Yung-Chin Hou
IPC分类号： H01L27/092 , H01L21/8238 , H01L23/485 , H01L27/02 , H01L29/423 , H01L29/66 , H01L29/78 , H01L29/06 , H01L29/49
摘要： An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

3. 发明授权

US09754881B2 Designed-based interconnect structure in semiconductor structure 有权
公开(公告)号：US09754881B2
公开(公告)日：2017-09-05
申请号：US15050087
申请日：2016-02-22
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Chih-Liang Chen , Chih-Ming Lai , Yung-Sung Yen , Kam-Tou Sio , Tsong-Hua Ou , Chun-Kuang Chen , Ru-Gun Liu , Shu-Hui Sung , Charles Chew-Yuen Young
IPC分类号： H01L27/118 , H01L23/528 , H01L23/522 , H01L27/02
CPC分类号： H01L23/528 , H01L23/5226 , H01L27/0207 , H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate. The gate structures follow the following equation: 0.2 ⁢ ⁢ P gate ⁢ ⁢ min + 0.35 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min - 20 0.2 ⁢ ⁢ L gate ⁢ ⁢ min + 0.8 ⁢ ⁢ H gate ⁢ ⁢ min - 5 × 0.3 ⁢ ⁢ L gate ⁢ ⁢ min + 0.3 ⁢ ⁢ H gate ⁢ ⁢ min + 5 38 ≤ 0.32 Pgate min is the minimum value among gate pitches of the gate structures, and Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

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