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1. 发明申请

US20220359308A1 Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same 有权
公开(公告)号：US20220359308A1
公开(公告)日：2022-11-10
申请号：US17815085
申请日：2022-07-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC分类号： H01L21/8238 , H01L21/306 , H01L27/11
摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

2. 发明授权

US12112989B2 Semiconductor device with tunable epitaxy structures and method of forming the same 有权
公开(公告)号：US12112989B2
公开(公告)日：2024-10-08
申请号：US17815085
申请日：2022-07-26
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC分类号： H01L21/8238 , H01L21/306 , H01L27/092 , H01L29/423 , H01L29/66 , H01L29/78 , H10B10/00
CPC分类号： H01L21/823814 , H01L21/30604 , H01L21/823821 , H01L27/0924 , H01L29/42392 , H01L29/6656 , H01L29/7848 , H10B10/12
摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

3. 发明授权

US08697539B2 Method of making lower parasitic capacitance FinFET 有权
标题翻译：制造较低寄生电容FinFET的方法
公开(公告)号：US08697539B2
公开(公告)日：2014-04-15
申请号：US13719460
申请日：2012-12-19
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Chih-Hsiang Huang , Chia-Pin Lin
IPC分类号： H01L29/76
CPC分类号： H01L21/76224 , H01L21/823431 , H01L29/66795 , H01L29/7843 , H01L29/7853
摘要： An integrated circuit device includes a gate region extending above a semiconductor substrate and extending in a first longitudinal direction. A first fin has a first sidewall that extends in a second longitudinal direction above the semiconductor substrate such that the first fin intersects the gate region. A second fin has a second sidewall extending in the second direction above the semiconductor substrate such that the second fin intersects the gate region. A shallow trench isolation (STI) region is formed in the semiconductor substrate between the first and second sidewalls of the first and second fins. A conductive layer disposed over the first insulating layer and over top surfaces of the first and second fins. A first insulating layer is disposed between an upper surface of the STI region and a lower surface of the conductive layer to separate the STI region from the conductive layer.
摘要翻译：集成电路器件包括在半导体衬底上延伸并在第一纵向方向上延伸的栅极区域。第一翅片具有第一侧壁，其在半导体衬底上方的第二纵向方向上延伸，使得第一鳍片与栅极区域相交。第二鳍片具有在半导体衬底上方的第二方向上延伸的第二侧壁，使得第二鳍片与栅极区域相交。在第一和第二鳍片的第一和第二侧壁之间的半导体衬底中形成浅沟槽隔离（STI）区域。布置在所述第一绝缘层之上和所述第一和第二鳍片的顶表面之上的导电层。第一绝缘层设置在STI区的上表面和导电层的下表面之间，以将STI区与导电层分离。

4. 发明授权

US11949015B2 Mechanisms for growing epitaxy structure of finFET device 有权
公开(公告)号：US11949015B2
公开(公告)日：2024-04-02
申请号：US17885155
申请日：2022-08-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Szu-Chi Yang , Chih-Hsiang Huang
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/08 , H01L29/165 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/823431 , H01L21/823821 , H01L29/0847 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/165
摘要： A method includes following steps. A semiconductor fin is formed extending from a substrate. A gate structure is formed extending across the semiconductor fin. Recesses are etched in the semiconductor fin. Source/drain epitaxial structures are formed in the recesses in the semiconductor fin. Formation of each of the source/drain epitaxial structures comprises performing a first epitaxy growth process to form a bar-shaped epitaxial structure in one of the recesses, and performing a second epitaxy growth process to form a cladding epitaxial layer cladding on the bar-shaped epitaxial structure. The bar-shaped epitaxial structure has a lower phosphorous concentration than the cladding epitaxial layer.

5. 发明授权

US11581226B2 Semiconductor device with tunable epitaxy structures and method of forming the same 有权
公开(公告)号：US11581226B2
公开(公告)日：2023-02-14
申请号：US16938340
申请日：2020-07-24
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC分类号： H01L21/8238 , H01L21/306 , H01L27/11 , H01L27/092
摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

6. 发明申请

US20220416046A1 Semiconductor Device With Leakage Current Suppression And Method Of Forming The Same 有权
公开(公告)号：US20220416046A1
公开(公告)日：2022-12-29
申请号：US17721778
申请日：2022-04-15
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shang-Rong Li , Shih-Hao Lin , Wen-Chun Keng , Chih-Chuan Yang , Chih-Hsiang Huang , Ping-Wei Wang
IPC分类号： H01L29/423 , H01L29/786 , H01L21/8234
摘要： A method of manufacturing a semiconductor device includes forming a fin, the fin having an epitaxial portion and a base portion protruding from a substrate. Sidewalls of the base portion are tapered with respect to sidewalls of the epitaxial portion. The method also includes depositing a polymeric material on the sidewalls of the epitaxial portion, performing an etching process to modify a profile of the sidewalls of the base portion, such that the sidewalls of the base portion are laterally recessed with a narrowest width of the base portion located under a top surface of the base portion, removing the polymeric material from the sidewalls of the epitaxial portion, depositing an isolation feature on the sidewalls of the base portion, and forming a gate structure engaging the epitaxial portion.

7. 发明授权

US11437516B2 Mechanisms for growing epitaxy structure of finFET device 有权
公开(公告)号：US11437516B2
公开(公告)日：2022-09-06
申请号：US15381270
申请日：2016-12-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Szu-Chi Yang , Chih-Hsiang Huang
IPC分类号： H01L29/78 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/08 , H01L29/165
摘要： A semiconductor structure includes a gate structure disposed over a substrate, and a plurality of source/drain features disposed on the substrate and interposed by the gate structure. Each of the source/drain features includes a first doped source/drain region extended away from the substrate, and a second doped source/drain region disposed on top and side surfaces of the first doped source/drain region, in which a phosphorus doping concentration of the first doped source/drain region is lower than a doping concentration of the second doped source/drain region.

8. 发明申请

US20210098311A1 Semiconductor Device With Tunable Epitaxy Structures And Method Of Forming The Same 有权
公开(公告)号：US20210098311A1
公开(公告)日：2021-04-01
申请号：US16938340
申请日：2020-07-24
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Shih-Hao Lin , Tzu-Hsiang Hsu , Chong-De Lien , Szu-Chi Yang , Hsin-Wen Su , Chih-Hsiang Huang
IPC分类号： H01L21/8238 , H01L27/11 , H01L21/306
摘要： Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

9. 发明申请

US20180151737A1 MECHANISMS FOR GROWING EPITAXY STRUCTURE OF FINFET DEVICE 审中-公开
公开(公告)号：US20180151737A1
公开(公告)日：2018-05-31
申请号：US15381270
申请日：2016-12-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Szu-Chi Yang , Chih-Hsiang Huang
IPC分类号： H01L29/78 , H01L29/08 , H01L29/167 , H01L29/06 , H01L29/66 , H01L29/165
摘要： A semiconductor structure includes a gate structure disposed over a substrate, and a plurality of source/drain features disposed on the substrate and interposed by the gate structure. Each of the source/drain features includes a first doped source/drain region extended away from the substrate, and a second doped source/drain region disposed on top and side surfaces of the first doped source/drain region, in which a phosphorus doping concentration of the first doped source/drain region is lower than a doping concentration of the second doped source/drain region.

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